sprs439m.pdf

TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232Digital Signal Controllers(DSCs)Data ManualPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.Literature Number:SPRS439MJune 2007Revised August 2012TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320FSPRS439M JUNE 2007REVISED AUGUST 2012Contents1TMS320F2833x,TMS320F2823x DSCs.101.1Features.101.2Getting Started.112Introduction.122.1Pin Assignments.142.2Signal Descriptions.233Functional Overview.333.1Memory Maps.343.2Brief Descriptions.413.2.1C28x CPU.413.2.2Memory Bus(Harvard Bus Architecture).413.2.3Peripheral Bus.413.2.4Real-Time JTAG and Analysis.423.2.5External Interface(XINTF).423.2.6Flash.423.2.7M0,M1 SARAMs.423.2.8L0,L1,L2,L3,L4,L5,L6,L7 SARAMs.433.2.9Boot ROM.433.2.9.1Peripheral Pins Used by the Bootloader.443.2.10Security.443.2.11Peripheral Interrupt Expansion(PIE)Block.463.2.12External Interrupts(XINT1XINT7,XNMI).463.2.13Oscillator and PLL.463.2.14Watchdog.463.2.15Peripheral Clocking.463.2.16Low-Power Modes.463.2.17Peripheral Frames 0,1,2,3(PFn).473.2.18General-Purpose Input/Output(GPIO)Multiplexer.473.2.1932-Bit CPU-Timers(0,1,2).473.2.20Control Peripherals.483.2.21Serial Port Peripherals.483.3Register Map.493.4Device Emulation Registers.513.5Interrupts.523.5.1External Interrupts.563.6System Control.573.6.1OSC and PLL Block.583.6.1.1External Reference Oscillator Clock Option.593.6.1.2PLL-Based Clock Module.603.6.1.3Loss of Input Clock.613.6.2Watchdog Block.623.7Low-Power Modes Block.634Peripherals.644.1DMA Overview.644.232-Bit CPU-Timer 0,CPU-Timer 1,CPU-Timer 2.664.3Enhanced PWM Modules.684.4High-Resolution PWM(HRPWM).724.5Enhanced CAP Modules.734.6Enhanced QEP Modules.754.7Analog-to-Digital Converter(ADC)Module.774.7.1ADC Connections if the ADC Is Not Used.812ContentsCopyright 20072012,Texas Instruments IncorporatedTMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320FSPRS439M JUNE 2007REVISED AUGUST 20124.7.2ADC Registers.824.7.3ADC Calibration.834.8Multichannel Buffered Serial Port(McBSP)Module.834.9Enhanced Controller Area Network(eCAN)Modules(eCAN-A and eCAN-B).864.10Serial Communications Interface(SCI)Modules(SCI-A,SCI-B,SCI-C).914.11Serial Peripheral Interface(SPI)Module(SPI-A).954.12Inter-Integrated Circuit(I2C).984.13GPIO MUX.994.14External Interface(XINTF).1065Device Support.1085.1Device and Development Support Tool Nomenclature.1085.2Documentation Support.1105.3Community Resources.1156Electrical Specifications.1166.1Absolute Maximum Ratings.1166.2Recommended Operating Conditions.1176.3Electrical Characteristics.1176.4Current Consumption.1186.4.1Reducing Current Consumption.1206.4.2Current Consumption Graphs.1216.4.3Thermal Design Considerations.1226.5Emulator Connection Without Signal Buffering for the DSP.1236.6Timing Parameter Symbology.1246.6.1General Notes on Timing Parameters.1246.6.2Test Load Circuit.1246.6.3Device Clock Table.1256.7Clock Requirements and Characteristics.1266.8Power Sequencing.1276.8.1Power Management and Supervisory Circuit Solutions.1286.9General-Purpose Input/Output(GPIO).1316.9.1GPIO-Output Timing.1316.9.2GPIO-Input Timing.1326.9.3Sampling Window Width for Input Signals.1336.9.4Low-Power Mode Wakeup Timing.1346.10Enhanced Control Peripherals.1396.10.1Enhanced Pulse Width Modulator(ePWM)Timing.1396.10.2Trip-Zone Input Timing.1396.10.3High-Resolution PWM Timing.1406.10.4Enhanced Capture(eCAP)Timing.1406.10.5Enhanced Quadrature Encoder Pulse(eQEP)Timing.1416.10.6ADC Start-of-Conversion Timing.1426.11External Interrupt Timing.1426.12I2C Electrical Specification and Timing.1436.13Serial Peripheral Interface(SPI)Timing.1436.13.1Master Mode Timing.1436.13.2SPI Slave Mode Timing.1486.14External Interface(XINTF)Timing.1516.14.1USEREADY=0.1516.14.2Synchronous Mode(USEREADY=1,READYMODE=0).1526.14.3Asynchronous Mode(USEREADY=1,READYMODE=1).1536.14.4XINTF Signal Alignment to XCLKOUT.1556.14.5External Interface Read Timing.1566.14.6External Interface Write Timing.158Copyright 20072012,Texas Instruments IncorporatedContents3TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232SPRS439M JUNE 2007REVISED AUGUST 6.14.7External Interface Ready-on-Read Timing With One External Wait State.1606.14.8External Interface Ready-on-Write Timing With One External Wait State.1636.14.9XHOLD and XHOLDA Timing.1666.15On-Chip Analog-to-Digital Converter.1696.15.1ADC Power-Up Control Bit Timing.1706.15.2Definitions.1716.15.3Sequential Sampling Mode(Single-Channel)(SMODE=0).1726.15.4Simultaneous Sampling Mode(Dual-Channel)(SMODE=1).1736.15.5Detailed Descriptions.1746.16Multichannel Buffered Serial Port(McBSP)Timing.1756.16.1McBSP Transmit and Receive Timing.1756.16.2McBSP as SPI Master or Slave Timing.1786.17Flash Timing.1826.18Migrating Between F2833x Devices and F2823x Devices.1847L-to-M Revision History.1858K-to-L Revision History.1869Thermal and Mechanical Data.1874ContentsCopyright 20072012,Texas Instruments IncorporatedTMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320FSPRS439M JUNE 2007REVISED AUGUST 2012List of Figures2-1F2833x,F2823x 176-Pin PGF/PTP LQFP(Top View).142-2F2833x,F2823x 179-Ball ZHH MicroStar BGA(Upper Left Quadrant)(Bottom View).162-3F2833x,F2823x 179-Ball ZHH MicroStar BGA(Upper Right Quadrant)(Bottom View).172-4F2833x,F2823x 179-Ball ZHH MicroStar BGA(Lower Left Quadrant)(Bottom View).182-5F2833x,F2823x 179-Ball ZHH MicroStar BGA(Lower Right Quadrant)(Bottom View).192-6F2833x,F2823x 176-Ball ZJZ Plastic BGA(Upper Left Quadrant)(Bottom View).202-7F2833x,F2823x 176-Ball ZJZ Plastic BGA(Upper Right Quadrant)(Bottom View).212-8F2833x,F2823x 176-Ball ZJZ Plastic BGA(Lower Left Quadrant)(Bottom View).222-9F2833x,F2823x 176-Ball ZJZ Plastic BGA(Lower Right Quadrant)(Bottom View).223-1Functional Block Diagram.343-2F28335,F28235 Memory Map.363-3F28334,F28234 Memory Map.373-4F28332,F28232 Memory Map.373-5External and PIE Interrupt Sources.533-6External Interrupts.533-7Multiplexing of Interrupts Using the PIE Block.543-8Clock and Reset Domains.573-9OSC and PLL Block Diagram.583-10Using a 3.3-V External Oscillator.593-11Using a 1.9-V External Oscillator.593-12Using the Internal Oscillator.593-13Watchdog Module.624-1DMA Functional Block Diagram.654-2CPU-Timers.664-3CPU-Timer Interrupt Signals and Output Signal.664-4Time-Base Counter Synchronization Scheme 3.684-5ePWM Submodules Showing Critical Internal Signal Interconnections.714-6eCAP Functional Block Diagram.734-7eQEP Functional Block Diagram.754-8Block Diagram of the ADC Module.784-9ADC Pin Connections With Internal Reference.794-10ADC Pin Connections With External Reference.804-11McBSP Module.844-12eCAN Block Diagram and Interface Circuit.874-13eCAN-A Memory Map.884-14eCAN-B Memory Map.894-15Serial Communications Interface(SCI)Module Block Diagram.944-16SPI Module Block Diagram(Slave Mode).974-17I2C Peripheral Module Interfaces.984-18GPIO MUX Block Diagram.1004-19Qualification Using Sampling Window.1054-20External Interface Block Diagram.1064-21Typical 16-bit Data Bus XINTF Connections.1074-22Typical 32-bit Data Bus XINTF Connections.1075-1Example of F2833x,F2823x Device Nomenclature.1096-1Typical Operational Current Versus Frequency(F28335,F28235,F28334,F28234).1226-2Typical Operational Power Versus Frequency(F28335,F28235,F28334,F28234).122Copyright 20072012,Texas Instruments IncorporatedList of Figures5TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232SPRS439M JUNE 2007REVISED AUGUST 6-3Emulator Connection Without Signal Buffering for the DSP.1236-43.3-V Test Load Circuit.1246-5Clock Timing.1276-6Power-on Reset.1296-7Warm Reset.1306-8Example of Effect of Writing Into PLLCR Register.1316-9General-Purpose Output Timing.1326-10Sampling Mode.1326-11General-Purpose Input Timing.1336-12IDLE Entry and Exit Timing.1346-13STANDBY Entry and Exit Timing Diagram.1366-14HALT Wake-Up Using GPIOn.1386-15PWM Hi-Z Characteristics.1396-16ADCSOCAO or ADCSOCBO Timing.1426-17External Interrupt Timing.1426-18SPI Master Mode External Timing(Clock Phase=0).1456-19SPI Master Mode External Timing(Clock Phase=1).1476-20SPI Slave Mode External Timing(Clock Phase=0).1496-21SPI Slave Mode External Timing(Clock Phase=1).1506-22Relationship Between XTIMCLK and SYSCLKOUT.1546-23Example Read Access.1576-24Example Write Access.1596-25Example Read With Synchronous XREADY Access.1616-26Example Read With Asynchronous XREADY Access.1626-27Write With Synchronous XREADY Access.1646-28Write With Asynchronous XREADY Access.1656-29External Interface Hold Waveform.1676-30XHOLD/XHOLDA Timing Requirements(XCLKOUT=1/2 XTIMCLK).1686-31ADC Power-Up Control Bit Timing.1706-32ADC Analog Input Impedance Model.1716-33Sequential Sampling Mode(Single-Channel)Timing.1726-34Simultaneous Sampling Mode Timing.1736-35McBSP Receive Timing.1776-36McBSP Transmit Timing.1776-37McBSP Timing as SPI Master or Slave:CLKSTP=10b,CLKXP=0.1786-38McBSP Timing as SPI Master or Slave:CLKSTP=11b,CLKXP=0.1796-39McBSP Timing as SPI Master or Slave:CLKSTP=10b,CLKXP=1.1806-40McBSP Timing as SPI Master or Slave:CLKSTP=11b,CLKXP=1.1816List of FiguresCopyright 20072012,Texas Instruments IncorporatedTMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320FSPRS439M JUNE 2007REVISED AUGUST 2012List of Tables2-1F2833x Hardware Features.122-2F2823x Hardware Features.132-3Signal Descriptions.233-1Addresses of Flash Sectors in F28335,F28235.383-2Addresses of Flash Sectors in F28334,F28234.383-3Addresses of Flash Sectors in F28332,F28232.383-4Handling Security Code Locations.393-5Wait-states.403-6Boot Mode Selection.433-7Peripheral Bootload Pins.443-8Peripheral Frame 0 Registers.493-9Peripheral Frame 1 Registers.493-10Peripheral Frame 2 Registers.503-11Peripheral Frame 3 Registers.503-12Device Emulation Registers.513-13PIE Peripheral Interrupts.543-14PIE Configuration and Control Registers.553-15External Interrupt Registers.563-16PLL,Clocking,Watchdog,and Low-Power Mode Registers.583-17PLL Settings.603-18CLKIN Divide Options.603-19Possible PLL Configuration Modes.613-20Low-Power Modes.634-1CPU-Timers 0,1,2 Configuration and Control Registers.674-2ePWM Control and Status Registers(Default Configuration in PF1).694-3ePWM Control and Status Registers(Remapped Configuration in PF3-DMA-Accessible).704-4eCAP Control and Status Registers.744-5eQEP Control and Status Registers.764-6ADC Registers.824-7McBSP Register Summary.854-83.3-V eCAN Transceivers.874-9CAN Register Map.904-10SCI-A Registers.924-11SCI-B Registers.924-12SCI-C Registers.934-13SPI-A Registers.964-14I2C-A Registers.994-15GPIO Registers.1014-16GPIO-A Mux Peripheral Selection Matrix.1024-17GPIO-B Mux Peripheral Selection Matrix.1034-18GPIO-C Mux Peripheral Selection Matrix.1044-19XINTF Configuration and Control Register Mapping.1075-1TMS320 x2833x,2823x Peripheral Selection Guide.1106-1TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT.1186-2TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT.1196-3Typical Current Consumption by Various Peripherals(at 150 MHz).1206-4Clocking and Nomenclature(150-MHz Devices).125Copyright 20072012,Texas Instruments IncorporatedList of Tables7TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232SPRS439M JUNE 2007REVISED AUGUST 6-5Clocking and Nomenclature(100-MHz Devices).1256-6Input Clock Frequency.1266-7XCLKIN Timing Requirements PLL Enabled.1266-8XCLKIN Timing Requirements PLL Disabled.1266-9XCLKOUT Switching Characteristics(PLL Bypassed or Enabled).1266-10Power Management and Supervisory Circuit Solutions.1286-11Reset(XRS)Timing Requirements.1306-12General-Purpose Output Switching Characteristics.1316-13General-Purpose Input Timing Requirements.1326-14IDLE Mode Timing Requirements.1346-15IDLE Mode Switching Characteristics.1346-16STANDBY Mode Timing Requirements.1356-17STANDBY Mode Switching Characteristics.1356-18HALT Mode Timing Requirements.1376-19HALT Mode Switching Characteristics.1376-20ePWM Timing Requirements.1396-21ePWM Switching Characteristics.1396-22Trip-Zone Input Timing Requirements.1396-23High-Resolution PWM Characteristics at SYSCLKOUT=(60150 MHz).1406-24Enhanced Capture(eCAP)Timing Requirement.1406-25eCAP Switching Characteristics.1406-26Enhanced Quadrature Encoder Pulse(eQEP)Timing Requirements.1416-27eQEP Switching Characteristics.1416-28External ADC Start-of-Conversion Switching Characteristics.1426-29External Interrupt Timing Requirements.1426-30External Interrupt Switching Characteristics.1426-31I2C Timing.1436-32SPI Master Mode External Timing(Clock Phase=0).1446-33SPI Master Mode External Timing(Clock Phase=1).1466-34SPI Slave Mode External Timing(Clock Phase=0).1486-35SPI Slave Mode External Timing(Clock Phase=1).1506-36Relationship Between Parameters Configured in XTIMING and Duration of Pulse.1516-37XINTF Clock Configurations.1546-38External Interface Read Timing Requirements.1566-39External Interface Read Switching Characteristics.1566-40External Interface Write Switching Characteristics.1586-41External Interface Read Switching Characteristics(Ready-on-Read,1 Wait State).1606-42External Interface Read Timing Requirements(Ready-on-Read,1 Wait State).1606-43Synchronous XREADY Timing Requirements(Ready-on-Read,1 Wait State).1606-44Asynchronous XREADY Timing Requirements(Ready-on-Read,1 Wait State).1606-45External Interface Write Switching Characteristics(Ready-on-Write,1 Wait State).1636-46Synchronous XREADY Timing Requirements(Ready-on-Write,1 Wait State).1636-47Asynchronous XREADY Timing Requirements(Ready-on-Write,1 Wait State).1636-48XHOLD/XHOLDA Timing Requirements(XCLKOUT=XTIMCLK).1676-49XHOLD/XHOLDA Timing Requirements(XCLKOUT=1/2 XTIMCLK).1686-50ADC Electrical Characteristics(over recommended operating conditions).1696-51ADC Power-Up Delays.1706-52Typical Current Consumption for Different ADC Configurations(at 25-MHz ADCCLK).1708List of TablesCopyright 20072012,Texas Instruments IncorporatedTMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320FSPRS439M JUNE 2007REVISED AUGUST 20126-53Sequential Sampling Mode Timing.1726-54Simultaneous Sampling Mode Timing.1736-55McBSP Timing Requirements.1756-56McBSP Switching Characteristics.1766-57McBSP as SPI Master or Slave Timing Requirements(CLKSTP=10b,CLKXP=0).1786-58McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=10b,CLKXP=0).1786-59McBSP as SPI Master or Slave Timing Requirements(CLKSTP=11b,CLKXP=0).1796-60McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=11b,CLKXP=0).1796-61McBSP as SPI Master or Slave Timing Requirements(CLKSTP=10b,CLKXP=1).1806-62McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=10b,CLKXP=1).1806-63McBSP as SPI Master or Slave Timing Requirements(CLKSTP=11b,CLKXP=1).1816-64McBSP as SPI Master or Slave Switching Characteristics(CLKST