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Application ReportSPRAAD5March 2006Power Line Communication for Lighting ApplicationsUsing Binary Phase Shift Keying(BPSK)with a SingleDSP Controller.C2000-Systems ApplicationABSTRACTDSP controllers provide the on-chip peripherals and computational power needed toimplement various power electronics applications.A single-chip DSP controller allowsdesignerstoimplementmultiplefunctionssuchaspowerlinecommunication,power-factor correction,and inverter control,all needed for an overall dimmable lightingballast application.This application report presents a complete implementation of apower line modem following CEA-709 protocol using a single DSP.This paper is ashorterversionofthedetaileddocumentationofthisimplementationtitledTMS320C2000 Digital Signal Controller Power Line Communication Users Guide(SPRU714)which can be downloaded from http:.Contents1Introduction.22Implementation OF CEA-709 Protocol.33Experimental Results.74Conclusions.105References.10List of Figures1System Block Diagram.22CEA-709 PHY Block Diagram.33Frequency Effect of Under-Sampling.34Receive Signal Processing Block Diagram.45Tri-Level Waveform Construction.56Transmit Low-Pass Filter Amplifier.67DSP Controller Based Power Line Modem Hardware.78Received Waveform with Corresponding Demodulated Signal.89Serial Port GUI for Controlling the Power Line Modem Function.9SPRAAD5March 2006Power Line Communication for Lighting Applications Using Binary Phase Shift Keying(BPSK)with a Single DSP Controller1Submit Documentation F1IntroductionADCPWMSCISPIGPIOLine DriverReceive FilterAC blockingcapacitorCouplingTransformerADCPWMExtraPWMoutputsforInverterControlExtraADCinputsforsystemvariableDSPIntroductionPower line communication 1 is a cost-effective solution for communicating with and controlling a group ofstand alone units for many applications such as dimmable ballasts,e-metering,or motor control.Thereare various methods of implementing power line communication,and in many cases a dedicatedcommunication chip is utilized to implement the modem portion of the system.The application portion(ballast,e-metering,etc.)typically utilize a second controller.This two-chip implementation is a goodsolution for many systems,however,cost-sensitive applications like dimmable lighting ballasts can furtherbenefit from additional system integration.An advanced DSP controller can offer this system integration bycombining the power line modem functionality as well as system operations using the on chip peripheralsof the device.The DSP controllers can implement the complete modem function in software and canutilize the on-chip power electronics peripherals to receive and transmit over the power line with an analogfront end interface.The DSP controller can also implement other system functions like power-factorcorrection and inverter control for ballast operations by utilizing the extra MIPS and the on-chip peripheralset,thus offering integration for lower system cost.This application note presents a complete software and hardware implementation of a power line modemconforming to the CEA-7092 protocol using a single fixed-point DSP controller.The paper presents thedetailed analog front end design necessary for a robust receive and transmit operation.Finally,thehardware implementation of a complete system is presented as a design reference.More detaileddocumentation of this implementation can be found at http:/ titled TMS320C2000 Digital SignalController Power Line Communication Users Guide,SPRU714.Figure 1.System Block DiagramA system block diagram is shown in Figure 1.A single fixed-point DSP(TMS320F28123)is utilized toimplement the complete modem function.This particular DSP provides 150 MIPS of computationalcapability.Signal sensing is provided using an on-chip analog-to-digital converter with 12 MSPSconversion speed with 12 bits of resolution.The DSP offers multiple PWM channels to accommodatepower line modem as well as other applications like inverter control or lighting ballast control.Two on-chip PWM outputs are utilized with a line driver for the transmit function of the modem.Oneanalog-to-digital(ADC)input is utilized to sample the band-pass input signal to implement the receivefunction of the modem.The band-pass filter is implemented using a discrete filter.An AC-blockingcapacitor and a coupling transformer complete the analog front end design of this interface.The remainingPWM channels and ADC inputs are utilized to control an inverter to show the potential of systemintegration with power line modem functionality.The DSP code combines the MAC,Link,Network,Transport and Application layers in the commandhandler portion of the software.Figure 2 shows a block diagram of the CEA-709 modem functionimplemented using a DSP controller.2Power Line Communication for Lighting Applications Using Binary Phase Shift Keying(BPSK)with a Single DSP ControllerSPRAAD5March 2006Submit Documentation FTX messageCRC calculationEncode data8b/10bTransmitmemory bufferBit rate ISRPWM controllerInternal ADC12bits/12mspsSample rate ISRDigital PLLAGCsinecosineCheck CRCRX messageAnalog processingLow passfilter&LineDriverBand-pass FilterCouplingnetworkPower Line2Implementation OF CEA-709 Protocol0FNFs3FN2Fs.FcarrierFcarrier-FsFcarrier+?FsImplementation OF CEA-709 ProtocolFigure 2.CEA-709 PHY Block DiagramThe implemented communication protocol is based on the CEA-709 Standard.The complete CEA 709protocol stack is a substantial topic and beyond the scope of this paper.This paper will primarily discussthe physical layer implementation.The CEA-709 communication system is defined with a carrier frequency of 131.579 kHz.Each transmittedbit consists of 24 cycles of a sine wave at the carrier frequency,resulting in a baud rate of 5.5 kbps.Thephase of each bit field can be set to 0 degrees to encode a“zero”bit or 180 degrees to encode a“one”bit.Signal Reception:The 131.5 kHz modulated signal is detected by first removing the 50/60 Hz power linevoltage at the coupling network and then filtering the signal with a second order active band-pass filter.This filter is constructed using an operational amplifier.The output of the band-pass filter is sampled byone channel of the DSPs analogto-digital converter.The signal sample sequence is processed by anFIR matched filter and the output of this filter is used to perform timing recovery and data detection.By sampling the received signal at 115 kHz,which is 21/24ths of the carrier frequency,the signal can bedown-sampled from 131.5 kHz to an intermediate frequency of 16.5 kHz.This operation can be describedas mixing or multiplying the incoming carrier sine wave signal with the sample rate clock.Themultiplication of two sine wave signals results in a signal containing the sum and difference of thefrequencies of the two sine waves.Figure 3 shows the manner in which the frequencies fold aroundmultiples of the Nyquist frequency.Figure 3.Frequency Effect of Under-SamplingThe resulting digital values from the under-sampled analog-to-digital conversion have a frequency contentof 16.5 kHz plus the additive noise from the communication channel.In operation,the DSP generates an interrupt at the completion of each ADC sample conversion.Eachsample is then compared to the output of the digital PLL to estimate the phase of the received signal.Atthe bit rate,5.5 kHz,the phase is determined.If the phase is less than 90 degrees then a“zero”isassumed to be received,otherwise a“one”is assumed to be received.SPRAAD5March 2006Power Line Communication for Lighting Applications Using Binary Phase Shift Keying(BPSK)with a Single DSP Controller3Submit Documentation FImplementation OF CEA-709 ProtocolThe received bit sequence is compared to the known bit pattern for the“bit sync”field which is sent at thebeginning of a transmitted data packet.When the bit sync pattern is recognized,the modem then beginslooking for the“word sync”pattern.The word sync pattern demarks the start of message data and alsodefined the polarity of the message data.After the data portion of the packet is determined and each bithas been detected,each 8-bit data byte is decoded from the 11-bit codeword for that byte.The parity bitfor each byte is compared to the calculated parity for the transmitted data.The data is passed on from thePHY layer to the MAC layer.If the CRC checksum calculated from the received data agrees with the CRCword that was transmitted,the message is passed on from the MAC/Link layer to the Network layer.Phase Detection:In order to detect the transmitted signal,“zero”or“one”,the phase of the 16.5 kHz IFsignal is detected in the discrete received signal values.This is done by first driving a digitalphase-lock-loop(PLL)with the received samples.When the output of the PLL is locked synchronouslywith the received signal,an estimate of the complex phase between the PLL and the received signal isgenerated by the PLL module.The real part of the complex phase is the cosine sum and will be either alarge positive value when a“zero”has been received or a large negative value when a“one”has beenreceived.The complex part of the phase is the sine sum.This represents the phase error and is fed backto the PLL to adjust the sine output so that it tracks the received signal.Figure 4.Receive Signal Processing Block DiagramFigure 4 shows the complete receive signal processing block diagram.An automatic gain control moduleis also added to increase the robustness of the system.The AGC module applies an applicable gain to thereceive signal by detecting the average magnitude of the receive signal.Signal Transmission:In this application the transmit signal is generated directly using the on-chip PWMmodule outputs of the DSP controller.Each bit is defined to be 24 cycles,so the PWM controller isallowed to run for 24 cycles and then an interrupt reassigns the PWM outputs based on the polarity of thenext bit being transmitted.To generate the transmit waveform,the message data to be transmitted ispassed from the Application layer to the Session layer,to the Transport layer,to the Network layer,to theMAC/Link layer,and then to the PHY.At the Link layer the CRC word for the message data is calculatedand appended to the data.The MAC layer holds the data until the PHY has determined if the channel isavailable.This is done by looking for the presence of the preamble pattern on the power line.PWM Generation for the Transmit Waveform:A tri-level signal waveform is generated by summing twoPWM outputs from the DSP controller.This tri-level waveform is then low-pass filtered to produce a sinewave.A tri-level waveform has much lower odd-harmonic energy than a standard two-level square wave.4Power Line Communication for Lighting Applications Using Binary Phase Shift Keying(BPSK)with a Single DSP ControllerSPRAAD5March 2006Submit Documentation F()?=?=12sinsin2sin4ntTnTwnTwnnTtfpppp(1)()()()()?=?=20202,1,nTTdtntfdtntfTHD(2).pwm1pwm1+pwm2width=4 clksperiod=12clks0 1 23 4 5 6 7 8 9 10 11.pwm2clk.width=4 clks()22222111CakRsakRCAakksvCakRAvaout+-+=(3)Implementation OF CEA-709 ProtocolDifferent pulse widths will produce different harmonic frequency content.In order to minimize harmonicsthat the filter needs to remove we need to use the optimum pulse width.This can be found by writing outthe formula for the Fourier series for a symmetric pulse where T is the fundamental frequency period andw is the pulse width.The total harmonic distortion(THD)can be expressed asUsing these equations and solving for the minimum total harmonic distortion(THD),the optimum pulsewidth is found to be approximately 37%of the period T.However,this does not take into account theeffect of the low pass filtering the waveform.If a second order low pass filter is applied to the waveform adifferent result is found.The Q of the 2nd order low pass filter used in simulations was set to 2.3.Thisvalue is a tradeoff between improved THD and the natural response time constant.With a large Q theTHD would be even better but the circuit rings from one transmitted bit time into the next bit time,resultingin inter-symbol interference.Therefore,the optimum design sets the digital positive and negative pulsewidths to 1/3 of the pulse period and sets the low pass filter corner frequency to the same frequency asthe digital pulse train.The 1/3 pulse width can easily be constructed using a timing clock that is 12 timesthe transmit waveform frequency.This is shown in Figure 5.The transmit sine wave is obtained fromthese PWM outputs by utilizing an analog circuit that sums the two signals and then low-pass filters theharmonics.Figure 5.Tri-Level Waveform ConstructionTransmit Amplifier:The transmit amplifier is based on a Sallen-Key filter,the transfer function for thiscircuit can be expressed as:where R1=kR,R2=R,C1=C,C2=aCSPRAAD5March 2006Power Line Communication for Lighting Applications Using Binary Phase Shift Keying(BPSK)with a Single DSP Controller5Submit Documentation FC1R3R4R1VrR2C2AVaVoVb2222www+=sQsvvaout(4)whereRCak1=w,()kkaQ+=1()11=+kk.(k is the ratio of R1to R2)Defining,R4=R,then3211111RRRR+=and13312RRRRR+=Further,defining the attenuation factor K such that13321RRRK+=.This is the attenuation of the input atRRRKKRKRRKRR=-=4321,2,()22222222112www+=+-+=sQsvKACaRsaRCAasvCKaRAvaaout(5)Implementation OF CEA-709 ProtocolFigure 6.Transmit Low-Pass Filter AmplifierFor an amplifier with a gain of 2,Voutcan be expressed as followsThe peaking in the filter is maximized when Q is maximized and Q is maximized when the quotientTherefore the resistors R1and R2in Figure 6 are typically set equal in a Sallen-Key filter circuit and the Qis set by adjusting the ratio of the capacitor values.The transmit amplifier has two inputs that add and filter the signal from the two PWM outputs of theprocessor.It is desirable to have a fair amount of peaking at the transmit frequency.The more peaking theamplifier provides at the transmit frequency,the more relative attenuation there will be at the harmonicfrequencies.Therefore we want to set the parallel combination of R1,R2and R3equal to R4so that a largeQ can easily be obtained.the first voltage node in the circuit.Then we can define the resistors in terms of R and K.Defining the capacitors as C1=C,C1=aC we can now express the transmit amplifier transfer function interms of A,K,a,R and C6Power Line Communication for Lighting Applications Using Binary Phase Shift Keying(BPSK)with a Single DSP ControllerSPRAAD5March 2006Submit Documentation FWhereRCa1=wand()AaaQ-+=12()()()12121181222-+-+-=AAQAQa(6)For an amplifier gain of A=2,and picking the smaller solution for a this reduces to:2221812QQa+-+=Finally,at s=0the transfer function gain is()KAQjjG-=0w.Now we have all the information we3Experimental ResultsExperimental ResultsFor a given Q we can solve for the capacitor ratio:need to define the component values for the transmit amplifier.The filter components are obtained usingthe above equations to design the analog front end of the modem.Figure 7.DSP Controller Based Power L