第31卷第3期厦门理工学院学报JournalofXiamenUniversityofTechnologyVol.31No.32023年6月Jun.2023基于UVM的报文验收滤波模块验证方法史雷萌，左石凯*，黄新栋，吕鑫，周犇，叶圣哲（厦门理工学院光电与通信工程学院，福建厦门361024）［摘要］针对当前芯片验证平台搭建速度慢和验证覆盖率收集困难的问题，提出一种基于通用验证方法学（UVM）的报文验收滤波模块验证方法。该方法利用Python脚本语言搭建UVM平台框架结构，引入随机事件种子并结合可约束随机测试技术收集验证覆盖率，实现报文验收滤波模块的验证。测试结果表明，该方法收集模块功能的验证覆盖率为100%，与Verilog语言搭建的验证平台相比，代码数据量减少94%，缩短验证平台搭建时间。［关键词］滤波模块；验证方法；通用验证方法学（UVM）；Python脚本；重用性；覆盖率［中图分类号］TN402［文献标志码］A［文章编号］1673-4432（2023）03-0017-05AVerificationMethodforUVM-BasedMessageAcceptanceFilteringModulesSHILeimeng,ZUOShikai*,HUANGXindong,LÜXin,ZHOUBen,YEShengzhe(SchoolofOptoelectronic&CommunicationEngineering,XiamenUniversityofTechnology,Xiamen361024,China)Abstract:Averificationmethodbasedonauniversalverificationmethodology(UVM)isproposedtoaddresstheproblemsofslowbuildingspeedanddifficultyincollectingverificationcoveragedataforthecurrentchipverificationplatform.ThemethodbuildstheframeworkstructureofthegenericverificationmethodologyplatformusingthePythonscriptinglanguage,andcollectsverificationcoveragedatawithrandomeventseedscombinedwithconstrainablerandomtestingtechniquestoachievetheverificationofthemessageacceptancefilteringmodule.Verificationresultsshowthatthemethodhas100%coverageofverificationformodulefunctionscollectedandreducestheamountofcodedataby94%comparedtotheverificationplatformbuiltinVeriloglanguage,thusreducingthetimeinbuildingtheverificationplatform.Keywords:filtermodule;verificationmethods;universalverificationmethodology(UVM);Pythonscripts;reusability;coverage早期的集成电路（integratedcircuit，IC）芯片开发工作复杂度较低，采用Verilog语言编写测试激励的方式能够满足大部分验证需求。随着IC芯片电路规模的增大，为了确保待验证模块功能的正确doi:10.19697/j.cn...
