射频芯片校准设计.pdf

1RFIC/IMS 2008 WSB-3 Arya BehzadRFIC/IMS 2008 WSB-3 Arya BehzadWSL-3Calibration Techniques for Wireless SoCsArya BehzadBroadcom CorporationSan Diego,CA2RFIC/IMS 2008 WSL-3 Arya BehzadOutlineWhy Calibrate?Calibration TechniquesResistor CalibrationRC Time Constant CalibrationVCO CalibrationAutomatic Frequency Control(Agile Frequency Offset Calibration)Quadrature Error and LO Feedthrough CalibrationLO Generation Amplitude Control System and CalibrationOther CalibrationsProcess Sensing and CalibrationTemperature Sensing and CalibrationPower Detector Calibration3RFIC/IMS 2008 WSL-3 Arya BehzadCalibrations&“Support”CircuitryRadio self-calibrations used to be considered as“nice to have”.Today radio self-calibrations have been recognized as absolutely essential.Design of the calibration algorithms and methodology is an integral part of the radio design,and not an after-thoughtChip level and system level auto-calibration is required for overcoming difficulties of integrated radio design,increasing chip and system yield and improving performance.Some examples:VCO tuningTx and Rx IQ CalibrationR-Calibration on bandgap blocksRC time constant calibrationRSSIsAgile center frequency correctionIntegrated temperature sensorTransmit LO feedthrough cancellationTSSIRx DC Offsets&High-Pass CornersProcess sensing4RFIC/IMS 2008 WSL-3 Arya BehzadTodays Radio/RF TechnologyMultiple Frequency Bands,Simultaneous Operation for multiple standards&Applications(WLAN,Bluetooth,RFID,)Rapid Real Time configuration/calibration:Optimum PerformancesMax/Best Yields Multiple Fab/Process,PackageNo Factory Cal or Pre-Stored Cal data needed,No Flash or SRAMReduce RF test timeCompensate over temperature(which factory-cal does not allow for)DSPProcessorProgramming/CalibrationBasebandPLL/LOGENAFE RXAnalog RXAFETXAnalog TXRF RXRF FERF TXPARF FE5RFIC/IMS 2008 WSL-3 Arya BehzadRadio Blocks are developed using a digitally controllable matrix of Passive devices(R,L,C)Actives devicesADCs&DACsSmall Controllers/DSPsRadio Calibration TechnologySwitching Resistor&CapacitorsIT/R controlGain settingLNA controlDigital Logic BlockADCDACDACDACOpenloopClosedLoop6RFIC/IMS 2008 WSL-3 Arya BehzadIntegrated Smart Radio TechnologyLOGenerationPLLFrac NAutomaticCalibrationControl andData InterfaceRF InputRF OutputControlI/Q OutputI/Q InputRadio Blocks are developed using a digitally controllable matrix of Passive devices,Actives devices,ADCs&DACs&Small Controllers/DSPsThese units can be digitally programmed/calibrated by local calibration EnginesThese units can be digitally programmed/calibrated through JTAG by basebandLong Term Agile/Real Time calibrationOptimizes overall performances over many frames or PacketsShort Term Cal,Optimizes overall performances over a frame or packet Accurate frequency response,center frequency,gainMaximum dynamic rangeMinimizing non-idealities,such as DC offsets,I/Q mismatches,feed-through,coupling7RFIC/IMS 2008 WSL-3 Arya BehzadReceiver Architecture w/CalibrationBandwidth and frequency response are set by programming R*CGain and current consumption are set by programming I*RRX DC offset and blocking can be calibrated globally and locallyLOI1GWRSSIOutIQLOQ1GDC Offset Canceller A UnitdBmRF Att 20 dBRef Lvl-15 dBmRef Lvl-15 dBmStart 0 HzStop 300 kHz30 kHz/RBW 5 kHzVBW 2 kHzSWT 76 ms2MA3MA1MA1VIEW2VIEW3VIEW4VIEW4MA -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15Date:12.FEB.2002 03:28:5979x100001101default79x1001100179x1001000179x100001101default79x1001100179x10010001RC&LC Calibration8RFIC/IMS 2008 WSL-3 Arya BehzadMulti-Band Transmitter w/CalibrationOutput level calibrationLO Leakage CalibrationGain calibrationBandwidth&frequency calibration/programmingLOI2GLOQ2GLOI5GLOQ5GAnalog InIQTSSI&PeakDetectorRC&LC Calibration0123456789101112131415Register 52 WriteMeasured Data on corner lot(Existing WLAN)-50.0-45.0-40.0-35.0-30.0-25.0-10.0-15.0-10.0LO Leakage(dBc)DAC bias is adjusted to create DC offset for LO Leakage Cal9RFIC/IMS 2008 WSL-3 Arya Behzad90o+TRANSCEIVER CHIPDIGITAL BASEBAND CHIP/HOSTDACDACADCADCDAC90oDACDACDACDACDACCalibration at power-up or between framesUse loop-back pathsDigital correction:I/Q mismatchLO leakageAnalog correctionDC offsetFilter cutoffRef:I.Bouras,et al,ISSCC 2003Example of Transceiver with Multiple Calibrations10RFIC/IMS 2008 WSL-3 Arya BehzadRequirements for WLAN TransmittersLow transmit error vector magnitude(EVM).High linearity.Small I/Q imbalance.Low local oscillator(LO)phase noise.Low local oscillator feed-through(LOFT).46dBFc=5.24GHz,FBB=1MHz,Vin=1VppdFIMFBB+FLOFLOBefore Cal.28.3dBFIMFBB+FLOFLOAfter Cal.29RFIC/IMS 2008 WSL-3 Arya BehzadConstellation DiagramEntire Tx Chain After CalibrationFc=5.24GHzPo=-5dBmEVM 52dBc.Gain range of 17.5dB in 2.5dB/step.LOFT and I/Q imbalance Cancellation.Calibration algorithm to separate RF and BB LOFT.LOFT better than 32dBc for all gain settings.Image better than 46dBc for all gain settings.EVM better than-40dB in A-band and-41dB in G-band with-5dBm output power.31RFIC/IMS 2008 WSL-3 Arya BehzadIQIQDET_OUTDIGITAL CHIP/HOSTRF ICD/AA/DA/DD/ACALIBRATIONSEQUENCECOMPUTERX I/QMISMATCH-0.5-0.50.00.50.00.5I/Q diagramBefore calibrationAfter calibrationIQRef:I.Bouras,et al,ISSCC 2003Rx IQ Calibration32RFIC/IMS 2008 WSL-3 Arya BehzadLO Generation and Distribution in a MIMO Transceiver 2LOI5GLOQ5G3.23.9GHzInteger-NSynthesizer4.85.9GHzgRx1aRx1gTx1aTx1aTx2gTx2aRx2gRx222Q path not shown33RFIC/IMS 2008 WSL-3 Arya BehzadRx IQ CalibrationSame Core MethodAfter Tx IQ has been calibrated,a SSB test tone is transmitted and coupled to the Rx inputThe downconverted I and Q signals at Rx BB are used to calibrate the Rx LO I and Q in digital BBTx1 output is used to calibrate Rx1 and Tx2 output is used to calibrate Rx2aRx1aTx1aTx2aRx2LORF INRF INRF OUTRF OUTLOLOLOLOBUF21BUF22(I,Q)(I,Q)(I,Q)(I,Q)The problem is that the loading of BUF21(BUF22)is different during calibration with normal Rx operationPost-calibration image rejection can be limited to-35dBc34RFIC/IMS 2008 WSL-3 Arya BehzadRx IQ CalibrationCross Core MethodInstead,couple calibrated Tx2 output to Rx1 input,with Tx1 OFF during calibrationLoading of BUF22 is now the same during calibration and normal Rx operationRepeat the procedure with Tx1 and Rx2 when done with(Tx2,Rx1)Post-calibration image rejection is better than -50dBcaRx1aTx1aTx2aRx2LORF INRF INRF OUTRF OUTLOLOLOLOBUF21BUF22(I,Q)(I,Q)(I,Q)(I,Q)Ref:A.Behzad,et al,ISSCC 2007,JSSC 200735RFIC/IMS 2008 WSL-3 Arya Behzad+PLL LO GenerationSWOptionalBPF TX BasebandRC&RcalibrationBalunJTAGBalunRX BasebandXOAFCSensors outRSSIs outRX_I outRX_Q out4 wires JTAGCrystalClock outAFC_I inAFC_Q inTX_I inTX_Q inRef:A.Behzad,et al,ISSCC 2003Transceiver with Agile Center Frequency Offset Correction(MMAFC)Also known as Mixed Mode Automatic Frequency Control of MMAFC36RFIC/IMS 2008 WSL-3 Arya Behzad-8.125 -.312 .312 8.125 MHzIdealOFDM Subcarriers withpayloadFrequency offsetFrequency offset+fadingFading HPF LPFfStandard requirement of 20PPM:214KHz of frequency offset at 5.35GHzNeed for Center Frequency Offset Correction37RFIC/IMS 2008 WSL-3 Arya BehzadPLL Frequency AdjustmentAdjusting PLL frequency to correct for Crystal frequency error is not viable as the settling time would be too slow38RFIC/IMS 2008 WSL-3 Arya BehzadTX RX fPLL/VCO 3.5 GHz1/220 MHz XtalIDACLPFRx LO=5.25+fAFCDACLPFQcossin fADCFrequency EstimationRadio Chip BB ChipTx LO=5.25+(f=0)Rx IRx QvcoTXLOff=23_afcvcoRXLOfff+=23_1.75 GHz+fRef:A.Behzad,et al,ISSCC 2003MMAFC Block Diagram39RFIC/IMS 2008 WSL-3 Arya BehzadLOFT+f(wanted)+2 f(HD2)+3 f(HD3)0.5fVCOf(image)fVCOVddfAFC_I LO_IGm1VGA1VGA2Mix5Mix1Mix2Gain control0.5fVCO_I fLOFT+2 f(HD2)+3 f(HD3)1.5fVCOf(image)VddLO_QGm3Gm4VGA3VGA4Mix6Mix3Mix4Gain control0.5fVCO_QfVCOfAFC_Q ff fwantedGm2Block Diagram of LO Generation Mixers40RFIC/IMS 2008 WSL-3 Arya BehzadVCO+VCO-VddAFCI+AFCI-LO_I+LO_I-Gm1+VGA1Gm2+VGA2AFCQ+AFCQ-1/2VCO_I+1/2VCO_I-1/2VCO_Q+1/2VCO_Q-Mix5Mix1 Mix2Simplified Schematic of LO Generation Mixers41RFIC/IMS 2008 WSL-3 Arya BehzadMulti-section Class AB Offset-Gm of MMAFC Mixer I_biasAFC_I+AFC_I-Gm_I+Gm_I-VGAGm_mainGm1Gm2Gm3Gm4Construction of Linearized Transconductance2.2m1.9mGm_overall SGm_linearization S Gm_main S-400m -200 m 0 200m 400mVin V38 S700 S6.97m6.91m1.9m0.3mGm_mainGm_outGm4Gm1Gm2Gm342RFIC/IMS 2008 WSL-3 Arya BehzadAFC PerformanceMultipath:200ns,-2dB,180deg;Frequency Offset:200kHzStart:-26 carrier index Stop:+26 carrierA:Ch1 Spectrum60%LinMag6%/div0%Span=36MHzA:Ch1 OFDM Err Vect SpectrumAFC DisabledAFC Enabled60%LinMag6%/div0%Span=36MHzA:Ch1 OFDM Err Vect SpectrumA:Ch1 SpectrumStart:-26 carrier index Stop:+26 carrierMMAFC Performance43RFIC/IMS 2008 WSL-3 Arya BehzadAFC DisabledAFC EnabledRX EVM:-24.3dB RX EVM:-28.4dBRx EVM Improved by 4.1dBA:Ch1 OFDM MeasA:Ch1 OFDM MeasMMAFC Performance44RFIC/IMS 2008 WSL-3 Arya BehzadVCO CalibrationCoverage over a wide frequency range is required for many standardsOne way to achieve this is to design a VCO with a high gain factor(Kvco)The problem with a high gain VCO is the sensitivity of the VCO to noise on the control line and the supplies,and hence often a poor phase noiseAn alternate method to achieve a wide tuning range while maintaining a low Kvcois to use banks of switch capacitors in the VCOThe switch capacitor setting sets the VCO to a frequency that is“close enough”and then the varactor is used in conjunction with the PLL to set the exact frequencyDue to process,temperature and supply variations,it is not sufficient to set the switch capacitor banks for a required channel based on a a-priori programmed lookup tableIt is essential to use an auto-calibration loop to ensure proper operation over PVT and to ensure the operation of the charge pump over a compliant voltage rangeThe auto-calibration can be done wit the PLL in open-loop mode,closed-loop mode,or a combination of the twoTradeoffs of calibration accuracy against calibration time need to be accounted for45RFIC/IMS 2008 WSL-3 Arya Behzad0.40.50.60.70.80.911.11.21.31.451005400VCO Control Voltage VVCO Output Frequency MHzVCO Tuning CurvesVCO switch capacitor tuning curves covering the lower U.S.802.11a band.The calibration algorithm selects the optimal curve such that the VCO can operate at a voltage around the middle of the charge pump compliance range.46RFIC/IMS 2008 WSL-3 Arya BehzadCompact&Power Efficient LOGENExtensive calibrations are utilized in this compact and power-efficient LO generation sub-systemSimplified block diagram shownRef:R.Rofoogaran,et al,RFIC 200847RFIC/IMS 2008 WSL-3 Arya BehzadGain-Boosted Inductively Loaded StageUtilized in the various sections of the calibrated LOGEN sub-systemSimplified schematic shown48RFIC/IMS 2008 WSL-3 Arya BehzadCalibrated LOGEN Gain Setting Output-4048121620-4004080120Temperature,CA Buffer Gain Setting Level(max=15,min=0)w/ACLw/o ACLGain setting of a representative buffer with and without the amplitude control loop calibrationWith ACL,lower settings are achieved at colder temperatures corresponding to lower power consumption4.9GHz,5.4GHz,5.9GHz4.9GHz5.4GHz5.9GHz49RFIC/IMS 2008 WSL-3 Arya BehzadResistor CalibrationOften a constant on-chip current is required,where the current varies minimally with process parametersA fairly accurate and process independent voltage can be easily synthesized on chip by using a bandgap circuit.A constant current can be synthesized if this voltage is applied to a process-independent resistorOften the resistors utilized in a vanilla CMOS process have high variationA calibration circuit is needed to compensate for this variationOne method would be to generate the required current by applying the bandgapvoltage on an external low tolerance resistorThis method would require one external resistor and one pin for each on chip calibrated current and is not efficientA better alternative is to use a state machine to equalize an on chip generated current(with a particular type of resistor)against the externally generated one,obtain the code,and then apply this code to all currents that require a constant current(and use the same type of resistor)on chipSince the sheet resistance of a resistor is the primary contributor to the resistance variation,and since sheet resistance is fairly constant across the chip,this method obtains the desired outcome with one external resistor and one extra pin50RFIC/IMS 2008 WSL-3 Arya BehzadFilter Bandwidth CalibrationOften a constant filter bandwidth is required for optimal pass-band response while providing proper ACIIf we consider a opamp-RC type filter,for example,the bandwidth would vary with varying on chip R and on chip C valuesOne(off-line)method to calibrate the bandwidth is to utilize a master-slave approachAn on-chip relaxation type RC-based oscillator synthesizes an approximate frequencyThe counts from this oscillator are compared against that of a known accurate oscillator(such as a crystal oscillator)The Rs or Cs of the relaxation oscillator are adjusted to achieve the desired countThe code for the adjusted R or C is obtained and then applied the filters which utilize the same type of Rs and Cs in their constructionOther more sophisticated techniques also exist for filter calibrations51RFIC/IMS 2008 WSL-3 Arya BehzadHighly Accurate Integrated Temp SenseCan be utilized to adjust parameters that are subject to temperature variations52RFIC/IMS 2008 WSL-3 Arya BehzadCalibrations Help Achieve Best-of-class Radio PerformanceRadio phase noise density and TX EVM is best of class(for all process technologies,not just CMOS)Digital calibration is key!Measured PN at transmitter output(5.24GHz)Measured Tx EVM(Po=-2dBm;-41dB 2.484GHz)TX Constellation(Po=-5dBm;EVM=-40dB 5.24GHz)Ref:A.Behzad,et al,ISSCC 2007,JSSC 200753RFIC/IMS 2008 WSL-3 Arya BehzadConclusionWe have only touched upon a few calibration techniques that are utilized today to achieve transceivers with outstanding performance,low cost,and high yieldMany,many additional calibrations are possible and being applied to various transceiversTransmit power calibrationsTemperature sensor based calibrationsPower amplifier linearizations and calibrationsLINC Amplifier based calibrationsReceiver IP3 and IP2 based calibrationsPolar transmitter one-point and two-point based calibrationsSWC/MRC based calibrationsBeam-former based calibrationsPipeline ADC digital background calibrations