静态时序分析与逻辑...pdf

BTS?2?BTS2003?4?Version 1.0?!?#$?%&()*+?,-./?0?%123?450?%673?0?%123?89:;0?%12Timing Analyzer3?0?%673?-Static Timing Analysis(STA)?AB?&?89CD45?EFG?H?IJKLMNOPQ?R?FG?STU?V?LMTWXY?Z?_abcdefg45?Mhi?45jklm?nopqrs?tuJ?vw89xygzbs&AB?|?100%?45?/?0timing closure3?-Static Timing Analysis(STA)?89?z?Jvw?+?/?/?(?a?/?)?“?Ru?Rfi“rs?R?fl?HH?lmY?C?89”?EDC?.?r?a?FG?IMT45.?.B?R?f?jk?-Static Timing Analysis(STA)?Synopsys?PrimeTime?Mentor Graphics?SST Velocity?N?IC?&Primetime?k?89&?Innoveda?Blast89?NFPGA?s?s?&?FPGA?89?&FPGA?JIC?&?ASIC?ASIC?(?FPGA?ASIC?ASIC?/?ASIC?(FPGA?FPGA?(FPGA?!#?ASIC?jk?6?vw.?.?89?=?=jk?!?#$?%?AB?F?0 3T=tCO+tDELAY+tSU$%&?T()*+,-./0$%&?T(?1234$5()*+6789:;?$%AB f=1/TDQDQCDCLKINPUTtCOtDELAYtSUOUT!/#?$(Setup/Hold time)?V0Setup time3tSU?R?z?PY“?V&?V0Hold time3tH?R?z?PY“?V&tSUtHDataClock!/#?$(Setup/Hold Time)Y#$?/?V?tSU-34$5?Setup time?(tH-EF$5?Hold time?tCO$%GHI$5?Clock-to-Output time?tMET 34$5?Setting time?:;G;?$5(J+K.LMN?AN42-Metastability in Altera Devices?%&(Timing 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read_verilog$QUARTUS_ROOTDIR/eda/synopsys/primetime/lib/apex20ke_ramslice_pt.v read_verilog snug_pt.vocurrent_design snuglink_design snugread_sdf snug_v.sdo?FGPrimeTimePrimeTime(Altera)*+,Script?create_clock“CLK”-period 4 waveform 0 2check_timingreport_analysis_coveragereport_timing?FGPrimeTimePrimeTime(Altera)*+,Script?FGPrimeTimePrimeTime?(Xilinx?-.FPGA?/01TIGset_false_path45MAXDELAYset_max_delay?FOFFSET OUTset_output_delay?FOFFSET INset_input_delay?FPERIODcreate_clock?R?UCF?SDC?SDC Synopsys Design ConstraintsUCF Xilinx User Constraints File?FGPrimeTime23?45clock delay 1+max data path-clock delay 2+tsu 6 clock period?FGPrimeTime23?45?$%?Global Clock?k?(Clock delay 6?B!0ns?Max data path!?+?tCO$5?+?5?cd$V?tsu!)*+?34$5Clock Delay 1=0nsClock Delay 2=0nsMax Data Path=tco of source reg+path between reg=1.449ns+.258ns=1.707nsWith 4ns clock period,the slack is 4ns-1.707ns=2.293ns?FGPrimeTime23?45?FGPrimeTime23?45?PrimeTimeab?METs1234$5VIOLATEDs?1278?45?FGPrimeTimeclock delay 1+minimum data delay clock delay 2 th 9 078?45?FGPrimeTime?$%?Global Clock?k?(Clock delay 6?B!0ns?Min data path!?+?tCO$5?+?5?cd$V?th!)*+?34$5Clock Delay 1=0nsClock Delay 2=0nsMinimum Data Path=tco of source reg+path between reg=1.449ns+.258ns=1.707nsIntrinsic hold time=1.284nsSlack is 1.707ns-1.284ns=0.493ns?FGPrimeTime78?45?FGPrimeTime78?45?PrimeTimeab?METs1234$5VIOLATEDs?12