STM32F10xxx的Cortex-M3编程手册英文文档.pdf

October 2009Doc ID 15491 Rev 21/137PM0056Programming manualSTM32F10 xxx Cortex-M3 programming manualThis programming manual provides information for application and system-level software developers.It gives a full description of the STM32F10 xxx Cortex-M3 processor programming model,instruction set and core peripherals.The STM32F10 xxx Cortex-M3 processor is a high performance 32-bit processor designed for the microcontroller market.It offers significant benefits to developers,including:Outstanding processing performance combined with fast interrupt handlingEnhanced system debug with extensive breakpoint and trace capabilitiesEfficient processor core,system and memoriesUltra-low power consumption with integrated sleep modesPlatform ContentsPM00562/137 Doc ID 15491 Rev 2Contents1About this document .81.1Typographical conventions.81.2List of abbreviations for registers .81.3About the STM32 Cortex-M3 processor and core peripherals.81.3.1System level interface .91.3.2Integrated configurable debug.91.3.3Cortex-M3 processor features and benefits summary.101.3.4Cortex-M3 core peripherals.112The Cortex-M3 processor.122.1Programmers model.122.1.1Processor mode and privilege levels for software execution.122.1.2Stacks .122.1.3Core registers .132.1.4Exceptions and interrupts .212.1.5Data types .212.1.6The Cortex microcontroller software interface standard(CMSIS).222.2Memory model.232.2.1Memory regions,types and attributes .242.2.2Memory system ordering of memory accesses.252.2.3Behavior of memory accesses.252.2.4Software ordering of memory accesses .262.2.5Bit-banding.272.2.6Memory endianness .292.2.7Synchronization primitives.302.2.8Programming hints for the synchronization primitives.312.3Exception model.322.3.1Exception states .322.3.2Exception types.322.3.3Exception handlers .342.3.4Vector table .352.3.5Exception priorities .352.3.6Interrupt priority grouping.362.3.7Exception entry and return .36PM0056ContentsDoc ID 15491 Rev 23/137 2.4Fault handling.392.4.1Fault types.392.4.2Fault escalation and hard faults.402.4.3Fault status registers and fault address registers .412.4.4Lockup.412.5Power management.412.5.1Entering sleep mode .422.5.2Wakeup from sleep mode .422.5.3The external event input .432.5.4Power management programming hints .433The Cortex-M3 instruction set .443.1Instruction set summary.443.2Intrinsic functions.493.3About the instruction descriptions .503.3.1Operands.503.3.2Restrictions when using PC or SP.513.3.3Flexible second operand .513.3.4Shift operations .523.3.5Address alignment.553.3.6PC-relative expressions.553.3.7Conditional execution.563.3.8Instruction width selection .583.4Memory access instructions.593.4.1ADR.593.4.2LDR and STR,immediate offset .603.4.3LDR and STR,register offset.623.4.4LDR and STR,unprivileged.633.4.5LDR,PC-relative .643.4.6LDM and STM .663.4.7PUSH and POP.673.4.8LDREX and STREX.693.4.9CLREX.703.5General data processing instructions.713.5.1ADD,ADC,SUB,SBC,and RSB.723.5.2AND,ORR,EOR,BIC,and ORN.74 ContentsPM00564/137 Doc ID 15491 Rev 23.5.3ASR,LSL,LSR,ROR,and RRX .753.5.4CLZ .763.5.5CMP and CMN.773.5.6MOV and MVN.783.5.7MOVT.793.5.8REV,REV16,REVSH,and RBIT.803.5.9TST and TEQ.813.6Multiply and divide instructions .823.6.1MUL,MLA,and MLS.823.6.2UMULL,UMLAL,SMULL,and SMLAL .843.6.3SDIV and UDIV .853.7Saturating instructions .863.7.1SSAT and USAT.863.8Bitfield instructions.873.8.1BFC and BFI .883.8.2SBFX and UBFX .883.8.3SXT and UXT.893.8.4Branch and control instructions.903.8.5B,BL,BX,and BLX.913.8.6CBZ and CBNZ .923.8.7IT .933.8.8TBB and TBH.953.9Miscellaneous instructions.963.9.1BKPT.973.9.2CPS.973.9.3DMB.983.9.4DSB.983.9.5ISB.993.9.6MRS.993.9.7MSR.1003.9.8NOP.1013.9.9SEV .1013.9.10SVC.1023.9.11WFE.1023.9.12WFI .1034Core peripherals .104PM0056ContentsDoc ID 15491 Rev 25/137 4.1About the STM32 core peripherals .1044.2Nested vectored interrupt controller(NVIC).1044.2.1The CMSIS mapping of the Cortex-M3 NVIC registers.1054.2.2Interrupt set-enable registers(NVIC_ISERx).1064.2.3Interrupt clear-enable registers(NVIC_ICERx).1074.2.4Interrupt set-pending registers(NVIC_ISPRx).1084.2.5Interrupt clear-pending registers(NVIC_ICPRx).1094.2.6Interrupt active bit registers(NVIC_IABRx).1104.2.7Interrupt priority registers(NVIC_IPRx).1114.2.8Software trigger interrupt register(NVIC_STIR).1124.2.9Level-sensitive and pulse interrupts.1124.2.10NVIC design hints and tips .1134.2.11NVIC register map.1144.3System control block(SCB).1154.3.1CPUID base register(SCB_CPUID).1154.3.2Interrupt control and state register(SCB_ICSR).1164.3.3Vector table offset register(SCB_VTOR).1184.3.4Application interrupt and reset control register(SCB_AIRCR).1194.3.5System control register(SCB_SCR).1204.3.6Configuration and control register(SCB_CCR).1214.3.7System handler priority registers(SHPRx).1224.3.8System handler control and state register(SCB_SHCSR).1244.3.9Configurable fault status register(SCB_CFSR).1264.3.10Hard fault status register(SCB_HFSR).1294.3.11Memory management fault address register(SCB_MMFAR).1304.3.12Bus fault address register(SCB_BFAR).1304.3.13System control block design hints and tips .1314.3.14SCB register map .1314.4SysTick timer(STK).1324.4.1SysTick control and status register(STK_CTRL).1324.4.2SysTick reload value register(STK_LOAD).1334.4.3SysTick current value register(STK_VAL).1344.4.4SysTick calibration value register(STK_CALIB).1344.4.5SysTick design hints and tips.1354.4.6SysTick register map.1355Revision history .136 List of tablesPM00566/137 Doc ID 15491 Rev 2List of tablesTable 1.Summary of processor mode,execution privilege level,and stack use options.13Table 2.Core register set summary.13Table 3.PSR register combinations.15Table 4.APSR bit definitions.16Table 5.IPSR bit definitions.17Table 6.EPSR bit definitions.18Table 7.PRIMASK register bit definitions.19Table 8.FAULTMASK register bit definitions.19Table 9.BASEPRI register bit assignments.20Table 10.CONTROL register bit definitions.20Table 11.Ordering of memory accesses.25Table 12.Memory access behavior.25Table 13.SRAM memory bit-banding regions.27Table 14.Peripheral memory bit-banding regions.27Table 15.C compiler intrinsic functions for exclusive access instructions.31Table 16.Properties of the different exception types.33Table 17.Exception return behavior.38Table 18.Faults.39Table 19.Fault status and fault address registers.41Table 20.Cortex-M3 instructions.44Table 21.CMSIS intrinsic functions to generate some Cortex-M3 instructions.49Table 22.CMSIS intrinsic functions to access the special registers.50Table 23.Condition code suffixes.57Table 24.Memory access instructions.59Table 25.Immediate,pre-indexed and post-indexed offset ranges.61Table 26.label-PC offset ranges .65Table 27.Data processing instructions.71Table 28.Multiply and divide instructions.82Table 29.Packing and unpacking instructions.87Table 30.Branch and control instructions .90Table 31.Branch ranges .91Table 32.Miscellaneous instructions.96Table 33.STM32 core peripheral register regions.104Table 34.Mapping of interrupts to the interrupt variables .105Table 35.IPR bit assignments.111Table 36.CMSIS functions for NVIC control .113Table 37.NVIC register map and reset values.114Table 38.Priority grouping.120Table 39.System fault handler priority fields.122Table 40.SCB register map and reset values.131Table 41.SysTick register map and reset values.135Table 42.Document revision history .136PM0056List of figuresDoc ID 15491 Rev 27/137 List of figuresFigure 1.STM32 Cortex-M3 implementation.9Figure 2.Processor core registers.13Figure 3.APSR,IPSR and EPSR bit assignments.15Figure 4.PSR bit assignments .15Figure 5.PRIMASK bit assignments.19Figure 6.FAULTMASK bit assignments .19Figure 7.BASEPRI bit assignments .20Figure 8.CONTROL bit assignments .20Figure 9.Memory map.23Figure 10.Bit-band mapping.28Figure 11.Little-endian example.29Figure 12.Vector table.35Figure 13.ASR#3 .53Figure 14.LSR#3.53Figure 15.LSL#3.54Figure 16.ROR#3.54Figure 17.RRX#3.54Figure 18.NVIC_IPRx register mapping.111Figure 19.CFSR subregisters.126 About this documentPM00568/137 Doc ID 15491 Rev 21 About this documentThis document provides the information required for application and system-level software development.It does not provide information on debug components,features,or operation.This material is for microcontroller software and hardware engineers,including those who have no experience of ARM products.1.1 Typographical conventionsThe typographical conventions used in this document are:1.2 List of abbreviations for registersThe following abbreviations are used in register descriptions:1.3 About the STM32 Cortex-M3 processor and core peripheralsThe Cortex-M3 processor is built on a high-performance processor core,with a 3-stage pipeline Harvard architecture,making it ideal for demanding embedded applications.The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design,providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division.italic Highlights important notes,introduces special terminology,denotes internal cross-references,and citations.Enclose replaceable terms for assembler syntax where they appear in code or code fragments.For example:LDRSB,#read/write(rw)Software can read and write to these bits.read-only(r)Software can only read these bits.write-only(w)Software can only write to this bit.Reading the bit returns the reset value.read/clear(rc_w1)Software can read as well as clear this bit by writing 1.Writing 0 has no effect on the bit value.read/clear(rc_w0)Software can read as well as clear this bit by writing 0.Writing 1 has no effect on the bit value.toggle(t)Software can only toggle this bit by writing 1.Writing 0 has no effect.Reserved(Res.)Reserved bit,must be kept at reset value.PM0056About this documentDoc ID 15491 Rev 29/137 Figure 1.STM32 Cortex-M3 implementationTo facilitate the design of cost-sensitive devices,the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities.The Cortex-M3 processor implements a version of the Thumb instruction set,ensuring high code density and reduced program memory requirements.The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture,with the high code density of 8-bit and 16-bit microcontrollers.The Cortex-M3 processor closely integrates a configurable nested interrupt controller(NVIC),to deliver industry-leading interrupt performance.The NVIC includes a non-maskable interrupt(NMI),and provides up to 256 interrupt priority levels.The tight integration of the processor core and NVIC provides fast execution of interrupt service routines(ISRs),dramatically reducing the interrupt latency.This is achieved through the hardware stacking of registers,and the ability to suspend load-multiple and store-multiple operations.Interrupt handlers do not require any assembler stubs,removing any code overhead from the ISRs.Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another.To optimize low-power designs,the NVIC integrates with the sleep modes,that include a deep sleep function that enables the STM32 to enter STOP or STDBY mode.1.3.1 System level interfaceThe Cortex-M3 processor provides multiple interfaces using AMBA technology to provide high speed,low latency memory accesses.It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls,system spinlocks and thread-safe Boolean data handling.1.3.2 Integrated configurable debugThe Cortex-M3 processor implements a complete hardware debug solution.This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug(SWD)port that is ideal for small package devices.ProcessorcoreEmbedded Trace MacrocellNVICDebug access portSerial wire viewerBus matrixCode interfaceSRAM and peripheral interfaceData watchpointsFlashpatchSTM32 Cortex-M3processorai15994 About this documentPM005610/137 Doc ID 15491 Rev 2For system trace the processor integrates an Instrumentation Trace Macrocell(ITM)alongside data watchpoints and a profiling unit.To enable simple and cost-effective profiling of the system events these generate,a Serial Wire Viewer(SWV)can export a stream of software-generated messages,data trace,and profiling information through a single pin.The optional Embedded Trace Macrocell(ETM)delivers unrivalled instruction trace capture in an area far smaller than traditional trace units,enabling many low cost MCUs to implement full instruction trace for the first time.1.3.3 Cortex-M3 processor features and benefits summaryTight integration of system peripherals reduces area and development costsThumb instruction set combines high code density with 32-bit performanceCode-patch ability for ROM system updatesPower control optimization of system componentsIntegrated sleep modes for low power consumptionFast code execution permits slower processor clock or increases sleep mode timeHardware division and fast multiplierDeterministic,high-performance interrupt handling for time-critical applicationsExtensive debug and trace capabilities:Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing.PM0056About this documentDoc ID 15491 Rev 211/137 1.3.4 Cortex-M3 core peripheralsThese are:Nested vectored interrupt controller The nested vectored interrupt controller(NVIC)is an embedded interrupt controller that supports low latency interrupt processing.System control block The system control block(SCB)is the programmers model interface to the processor.It provides system implementation information and system control,including configuration,control,and reporting of system exceptions.System timer The system timer,SysTick,is a 24-bit count-down timer.Use this as a Real Time Operating System(RTOS)tick timer or as a simple counter.The Cortex-M3 processorPM005612/137 Doc ID 15491 Rev 22 The Cortex-M3 processor2.1 Programmers modelThis section describes the Cortex-M3 programmers model.In addition to the individual core register descriptions,it contains information about the processor modes and privilege levels for software execution and stacks.2.1.1 Processor mode and privilege levels for software executionThe processor modes are:The privilege levels for software execution are:In Thread mode,the CONTROL register controls whether software execution is privileged or unprivileged,see CONTROL register on page 20.In Handler mode,software execution is always privileged.Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode.Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software.2.1.2 StacksThe processor uses a full descending stack.This means th