TMS320F281x Data Sheet (Rev. I).pdf

TMS320F2810,TMS320F2812Digital Signal ProcessorsData ManualLiterature Number:SPRS174IApril 2001 Revised July 2003ADVANCE INFORMATION concerns new products in the sampling orpreproduction phase of development.Characteristic data and otherspecifications are subject to change without notice.IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements,and other changes to its products and services at any time and to discontinueany product or service without notice.Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete.All products are sold subject to TIs termsand conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TIs standard warranty.Testing and other quality control techniques are used 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patents or other intellectual propertyof the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproductionof this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable forsuch altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice.TI is not responsible or liable for any such statements.Following are URLs where you can obtain information on other Texas Instruments products and applicationsolutions:ProductsApplicationsAA CA C MOptical N Address:Texas InstrumentsPost Office Box 655303 Dallas,Texas 75265Copyright 2003,Texas Instruments IncorporatediiiREVISION HISTORYREVISIONDATEPRODUCT STATUSHIGHLIGHTSDevice is now at the“TMP”stage of development(final silicon diethat conforms to the devices electrical specifications but has notcompleted quality and reliability verification)Added the following:Section 3.8.1,Loss of Input Clock(p.38)Section 7.12,Device Clock Table(p.80)Section 7.13,Clock Requirements and Characteristics(p.81)Section titled“Input Clock Requirements”now becomesSection 7.13.1(p.81)Section titled“Output Clock Characteristics”now becomesSection 7.13.2(p.82)Section 7.15,Event Manager Interface(p.87)Section 7.16,General-Purpose Input/Output(GPIO)Output Timings(p.91)Table 717,General-Purpose Input Timing Requirements(p.92)Figure 718,General-Purpose Input Timing(p.92)Figure 725,ADC Analog Input Impedance Model(p.109)Section 7.23,Flash Timings(p.117)Section 1,Features(p.1):Temperature Options feature:added GHH package to40C to 125C rangeIJuly 2003Advance InformationTable 21,Hardware Features(p.3):added Temperature Optionsadded footnotesUpdated descriptions of the following signals in Table 22,SignalDescriptions(p.7):X1/XCLKINADCINA7:0ADCINB7:0GPIOF14Table 31,Addresses of Flash Sectors in F2812(p.19):added address ranges“0 x3F 7F80”and“0 x3F 7FF5”Table 32,Addresses of Flash Sectors in F2810(p.19):added address ranges“0 x3F 7F80”and“0 x3F 7FF5”Table 33,Wait States(p.21):updated WAIT-STATES column for OTPupdated COMMENTS column for FlashSection 3.2.6,Flash(p.23):updated CAUTION note(Continued on next page)ivREVISION HISTORY(CONTINUED)REVISIONDATEPRODUCT STATUSHIGHLIGHTSSection 3.2.10,Security(p.24):updated first paragraphTable 37,Device Emulation Registers(p.29):updated description of DEVICEIDFigure 37,Multiplexing of Interrupts Using the PIE Block(p.33):added PIEACKxTable 312,PLL,Clocking,Watchdog,and Low-Power ModeRegisters(p.36):updated footnote about PLLCRSection 3.8,OSC and PLL Block(p.37):changed“The logic-high level in this case should not exceed1.8 V.”to“The logic-high level in this case should not exceedVDD.”Figure 310b,Recommended Crystal/Clock Connection(p.38):changed“Toggling 01.8 V”to“Toggling 0VDD”Figure 311,Watchdog Module(p.39):changed“Pull-up”to“Internal Pullup”Table 315,F2810 and F2812 Low-Power Modes(p.40):added“Debugger”to the EXIT column of the IDLE modeI(Continued)July 2003Advance InformationSection 3.12,Low-Power Modes Block(p.40):IDLE Mode:changed“LPMCR(LPM)bits”to“LPMCR0(LPM)bits”Section 4.2.7,Capture Unit(p.48):added feature about capture pinsSection 4.2.8,Quadrature-Encoder Pulse(QEP)Circuit(p.49):revised“With EXTCON register bits,.”paragraphSection 4.4,Enhanced Controller Area Network(eCAN)Module(p.53):added note about smallest bit rate possibleSection 4.8,GPIO Mux(p.67):replaced NOTE about input function of the GPIO pin with aCAUTION noteFigure 411,Modes of Operation(p.69):updated drawingupdated footnote about GPxDATSection 5,Development Support(p.70):updated Hardware Development Tools listUpdated Figure 51,TMS320 x28x Device Nomenclature(p.71)(Continued on next page)vREVISION HISTORY(CONTINUED)REVISIONDATEPRODUCT STATUSHIGHLIGHTSSection 7.1,Absolute Maximum Ratings(p.73):added VDDAIO to“Supply voltage range,VDDIO,VDDA1,VDDA2,and AVDDREFBG”added VDD1 to“Supply voltage range,VDD”added GHH package to S version of“Operating casetemperature ranges,TC”added footnote reference to“Operating case temperatureranges,TC”Section 7.2,Recommended Operating Conditions(p.73):added VDD1 to“Device supply voltage,CPU”added VDDAIO to“ADC supply voltage”split VIH into two rows:“All inputs except XCLKIN”and“XCLKIN(50 A max)”split VIL into two rows:“All inputs except XCLKIN”and“XCLKIN(50 A max)”moved Nf and NOTP to Section 7.23.1,RecommendedOperating Conditionsadded VDDAIO to footnote about power sequencingSection 7.4,Current Consumption by Power-Supply Pins OverRecommended Operating Conditions During Low-Power Modes at150-MHz SYSCLKOUT(p.74):updated tableadded CAUTION note about HALT and STANDBY modesI(Continued)July 2003Advance InformationSection 7.5,Power Sequencing Requirements(p.75):Option 2:added VDDAIO to“(VDDIO,VDD3VFL,VDDA1/VDDA2/AVDDREFBG)”Figure 71,F2812/F2810 Typical Power-Up and Power-DownSequence Option 2(p.76):updated footnote Dadded footnote EFigure 72,F2812/F2810 Typical Current Consumption(WithPeripheral Clocks Enabled)(p.77):updated graphadded footnotesUpdated Table 72,Typical Current Consumption by VariousPeripherals(at 150 MHz)(p.77)Section 7.8,Signal Transition Levels(p.78):first paragraph:replaced“to a maximum logic-low level of 0.8 V”with“to a maximum logic-low level of 0.4 V”added NOTE about referencing individual timing diagramsFigure 75,3.3-V Test Load Circuit(p.79):replaced diagramTable 73,TMS320F2812 Clock Table and Nomenclature(p.80):changed MAX tc(LCO)from 150 MHz to 75 MHz(Continued on next page)viREVISION HISTORY(CONTINUED)REVISIONDATEPRODUCT STATUSHIGHLIGHTSUpdated Table 75,XCLKIN Timing Requirements PLL Bypassedor Enabled(p.81)Updated Table 76,XCLKIN Timing Requirements PLL Disabled(p.81)Table 78,XCLKOUT Switching Characteristics(PLL Bypassed orEnabled)(p.82):deleted footnote about tc(CI)approaching added“H=0.5tc(XCO)”footnoteUpdated Table 79,Reset(XRS)Timing Requirements(p.83)Figure 77,Power-on Reset in Microcomputer Mode(XMP/MC=0)(p.84):updated figureadded footnote explaining why XCLKOUT=XCLKIN/8added footnote about the state of the GPIO pinsI(Continued)July 2003Advance InformationFigure 78,Power-on Reset in Microprocessor Mode(XMP/MC=1)(p.85):updated figureadded footnote explaining why XCLKOUT=XCLKIN/8added footnote about the state of the GPIO pinsFigure 79,Warm Reset in Microcomputer Mode(p.86):added tsu(XPLLDIS)parameterFigure 717,GPIO Input Qualifier Example Diagram forQUALPRD=1(p.92):updated footnote BTable 718,SPI Master Mode External Timings(Clock Phase=0)(p.93):added NOTE about internal clock prescalarsTable 719,SPI Master Mode External Timings(Clock Phase=1)(p.95):added NOTE about internal clock prescalarsTable 723,External Memory Interface Read Switching Characteris-tics for XCLKOUT=XTIMCLK(p.103):updated tablerevised footnote about timings for XCLKOUT=1/2 XTIMCLK(Continued on next page)viiREVISION HISTORY(CONTINUED)REVISIONDATEPRODUCT STATUSHIGHLIGHTSTable 724,External Memory Interface Read Timing Requirements(p.103):deleted“TBD”from MIN ta(A)deleted footnote about design simulation modelsrevised footnote with table referenceUpdated Figure 723,Example Read Access(p.104)Table 725,External Memory Interface Write Switching Characteris-tics for XCLKOUT=XTIMCLK(p.105):updated tablerevised footnote about timings for XCLKOUT=1/2 XTIMCLKrevised footnote with table referenceUpdated Figure 724,Example Write Access(p.106)Table 726,DC Specifications(p.108):updated tableadded footnote about 12.5-MHz ADCCLKadded footnote about the SYSCLKOUT value and the ADC clockvalueI(Continued)July 2003Advance InformationTable 727(p.109):changed title from“AC Specifications”to“AC Specifications(PRELIMINARY DATA)”revised footnoteSection 7.21.3(p.109):changed title from“Current Consumption for Different ADCConfigurations”to“Current Consumption for Different ADCConfigurations(at 25-MHz ADCCLK)”updated tableFigure 727,Sequential Sampling Mode(Single-Channel)Timings(p.111):corrected ADC Event Trigger waveformTable 731,McBSP Timing Requirements(p.114):updated tablerevised footnotesTable 732,McBSP Switching Characteristics(p.115):updated tablerevised“P=1/CLKG in ns”footnoteRemoved information is available in Reference GuidesviiiREVISION HISTORY(CONTINUED)REVISIONDATEPRODUCT STATUSHIGHLIGHTSSection 1,Featuresadded package information to the Temperature Options featureUpdated the descriptions of the following signals in Table 22,Signal Descriptions:X1/XCLKIN,XCLKOUT,TESTSEL,XRS,TEST1,TEST2,ADCREFM,ADCBGREFIN,VDD,GPIOF14Table 22,Signal Descriptionsupdated footnote about typical drive strengthHMarch 2003Advance InformationUpdated the following sections:Section 3.2.19,32-Bit CPU-Timers(0,1,2)Section 3.9,PLL-Based Clock Module:replaced“4096 XCLKIN cycles”with“131072 XCLKINcycles”Section 3.12,Low-Power Modes Blockadded note about state of output pinsSection 4.2,Event Manager Modules(EVA,EVB)Section 4.2.3,Programmable Deadband GeneratorSection 4.3,Enhanced Analog-to-Digital Converter(ADC)Modulein paragraph starting with“To obtain the specified accuracy ofthe ADC,proper.”,changed“the ADC module power pins(such as VCCA,VREFHI,and VSSA)”to“the ADC modulepower pins(VDDA1/VDDA2,AVDDREFBG)”Section 4.8,GPIO Muxadded note below Figure 411,Modes of OperationSection 5,Development SupportSection 6,Documentation SupportSection 7.1,Absolute Maximum Ratingsadded AVDDREFBG to“Supply voltage range”changed“Operating free-air temperature ranges,TA”to“Operating case temperature ranges,TC”added package information to“Operating case temperatureranges,TC”added footnote about long-term high-temperature storageand/or extended use at maximum recommended operatingconditionsSection 7.2,Recommended Operating Conditionsremoved 0 V from the MIN and MAX columns of VSSadded AVDDREFBG to“ADC supply voltage”changed“TA,Free-air temperature”to“TC,Case temperature”revised and footnotesSection 7.3,Electrical Characteristics Over RecommendedOperating ConditionsSection 7.4,Current Consumption by Power-Supply Pins OverRecommended Operating Conditions DuringLow-Power Modes at 150-MHz SYSCLKOUTrevised footnote(Continued on next page)ixREVISION HISTORY(CONTINUED)REVISIONDATEPRODUCT STATUSHIGHLIGHTSUpdated the following sections:Section 7.5,Power Sequencing Requirements:Option 1:changed VDDA1/VDDA2 toVDDA1/VDDA2/AVDDREFBGOption 2:changed VDDA1/VDDA toVDDA1/VDDA2/AVDDREFBGBGPower-Down Sequencing:changed“(8 s,typical)”to“(8 s,minimum)”Section 7.18.1,Absolute Maximum Ratingsadded AVDDREFBG to supply voltage rangeadded footnote about diode clamp protectionSection 7.18.3,Current Consumption for Different ADCConfigurationsadded footnote defining IDDASection 7.18.5.1,Reference Voltagereplaced“VREFP”with“ADCVREFP”replaced“VREFM”with“ADCVREFM”H(Continued)March 2003Advance InformationUpdated the following figures:Figure 32,F2812 Memory Mapchanged“0 x00 1000”to“0 x00 0E00”Figure 33,F2810 Memory Mapchanged“0 x00 1000”to“0 x00 0E00”Figure 313,Watchdog Moduleadded WDRST and removed note about silicon revisionimplementationrevised footnote about WDRST signalFigure 42,CPU-Timer Interrupts Signals and Output Signal:updated CPU-Timer 1 blockFigure 411,Modes of Operationdeleted the Pre-Scale blockrevised footnote about qualification of selected input signalsFigure 77,Power-on Reset in Microcomputer Mode(XMP/MC=0)added footnote defining VDDAnFigure 710,Effect of Writing Into PLLCR Registerreplaced“4096 XCLKIN Cycles”with“131072 XCLKINCycles”revised footnote(Continued on next page)xREVISION HISTORY(CONTINUED)REVISIONDATEPRODUCT STATUSHIGHLIGHTSHUpdated the following tables:Table 37,Device Emulation RegistersTable 39,DEVICEID Register Bit DefinitionsTable 316,Interrupt Vector Table MappingTable 77,XCLKOUT Switching Characteristics(PLL Bypassedor Enabled)changed MAX tp from 4096tc(CI)ns to 131072tc(CI)nsrevised footnote about future silicon revisionsTable 717,DC Specifications:deleted TEST CONDITIONS columnchanged“Accuracy,VREFP”to“Accuracy,ADCVREFP”changed“Accuracy,VREFM”to“Accuracy,ADCVREFM”added MIN and MAX values for“Input voltage difference,ADCREFP ADCREFM”added footnote about internal band gap referenceTable 719,ADC Power-Up Delays:changed MIN and TYP values of both parametersH(Continued)March 2003Advance InformationAdded the following:Section 7.18.4,ADC Power-Up Control Bit TimingFigure 71,F2812/F2810 Typical Power-Up and Power-DownSequence Option 2Table 81,Thermal Resistance Characteristics for 179-GHHTable 82,Thermal Resistance Characteristics for 176-PGFTable 83,Thermal Resistance Characteristics for 128-PBKRemoved the following section(section number is that inRevision G):Section 3.11.1,Emulation ConsiderationsRemoved the following tables(table numbers are those inRevision G):Table 335,WDCNT