RS-422 和 RS485 标准概述与系统配置_英文.pdf

Application ReportSLLA070DJune 2002Revised May 2010RS-422 and RS-485 Standards Overview and SystemConfigurationsManny Soltero,Jing Zhang,and Chris Cockril.HPA-Industrial InterfaceUpdated by Kevin Zhang,Clark Kinnaird,and Thomas Kugelstadt.ABSTRACTANSI TIA/EIA-422 and TIA/EIA-485 standards,commonly known as RS-422 and RS-485,respectively,specifybalanceddata-transmissionschemesfortransmittingdataoverlongdistancesinnoisyenvironments.These standards are compared,and their basic differences and similarities are discussed.Techniques for impedance matching to minimize line reflections in several applications are presented,withlaboratory test results.Contents1Introduction.32Overview of RS-422 and RS-485 Standards.32.1Selected RS-422 Electrical Specifications.32.2Selected RS-485 Electrical Specifications.93Failsafe Operation.123.1The Need for Failsafe Protection.123.2Internal Failsafe.133.3External Failsafe.134Suggested Termination and Grounding Techniques.134.1No Termination.134.2Parallel Termination.144.3AC Termination.164.4Multipoint Termination.174.5Ground Connections.185Typical System Configurations.215.1Daisy-Chain Configuration.215.2Bus and Stub Configuration.215.3Point-to-Point Configuration.226Summary Comparison of the Standards.226.1Common-Mode Range.226.2Line Contention.236.3Drive Current.237Conclusion.238Glossary.249Acknowledgment.2410References.24List of Figures1RS-422 Balanced-Voltage Digital-Interface Circuit.42RS-422 Open-Circuit Test Circuit.43RS-422 Output-Voltage Test Circuit.54RS-422 Short-Circuit Output-Current Test Circuit.55RS-422 Power-Off Output-Current Test Circuit.56RS-422 Test Circuit and Output-Signal Waveform.61SLLA070DJune 2002Revised May 2010RS-422 and RS-485 Standards Overview and System ConfigurationsCopyright 20022010,Texas Instruments I7RS-422 Input Receiver Test Circuit and I/V Plot.78RS-422 Input-Sensitivity Test Circuit and Resultant Waveform.89RS-485 Balanced-Voltage Digital-Interface Circuit.910RS-485 U.L.Test Circuit and I/V Relationship.1011RS-485 Open-Circuit Test Circuit.1012RS-485 Output-Voltage Test Circuit.1113RS-485 Output-Voltage Test Circuit With Common-Mode Loading.1114RS-485 Short-Circuit Output-Current Test Circuit.1115RS-485 Output-Signal Test Circuit.1216Differential Unterminated Configuration.1317Differential Unterminated-Driver Output Waveforms.1418Differential Unterminated-Receiver Input Waveforms.1419Differential Parallel-Terminated Configuration.1520Differential Parallel-Terminated Driver Output Waveforms.1521Differential Parallel-Terminated Receiver Input Waveforms.1622Differential AC-Terminated Configuration.1623Differential AC-Terminated Driver Output Waveforms.1724Differential AC-Terminated Receiver Input Waveforms.1725Differential Multipoint-Terminated Configuration.1826Grounding Configuration with Isolated Local Ground and PE.1927Grounding Configuration with Connected Local Ground and PE.1928Isolated Configuration.2029Daisy-Chain Connection.2130Stub Cables Connected to the Main Backbone.2231Point-to-Point Connection.22List of Tables1Input Sensitivity and Resultant Voltages of 422-Compliant Devices.82Input Sensitivity and Resultant Voltages of 485-Compliant Devices.123Summary of Termination Techniques.184Summary Comparison of RS-485 and RS-422 Specifications.232RS-422 and RS-485 Standards Overview and System ConfigurationsSLLA070DJune 2002Revised May 2010Copyright 20022010,Texas Instruments IIntroduction1IntroductionThe RS-422 and RS-485 standards,as they are known today,are balanced data-transmission schemesthat offer robust solutions for transmitting data over long distances and noisy environments.The officialtitles for these two standards are ANSI TIA/EIA-422 and TIA/EIA-485,respectively,and are revisedperiodically by the TR-30.2 DTE-DCE Interfaces and Protocols Subcommittee to the TelecommunicationsIndustry Association(TIA)TR-30 Data Transmission Systems and Equipment Committee.Foridentification,RS-422 and RS-485 suffice.This application report offers an overview of the RS-422 and RS-485 standards.While many specificationsare described in the official ANSI documents,only the most prevalent are discussed in this applicationreport.The purpose of this application report is to not duplicate the official documents,but to outline basicdifferences and similarities between the RS-422 and RS-485 standards.Major specifications are describedin detail and the two standards are compared.Because impedance matching is an important aspect ofdifferential data transmission in minimizing line reflections due to transmission-line effects,techniques forterminating different system applications are presented.Also,typical system configurations are taken intoconsideration for optimal application performance and cost constraints.2Overview of RS-422 and RS-485 StandardsOfficially,the RS-422 standards title is Electrical Characteristics of Balanced Voltage Digital InterfaceCircuits,and is published by the ANSI Telecommunication Industry Association/Electronic IndustriesAssociation(TIA/EIA).In the industry,the term RS-422 is commonly used rather than the official name,and this document does the same.RS-422 is specified as a simplex multidrop standard,which meansonly one driver and up to ten receivers can be attached to a bus.The RS-485 standards title is Electrical Characteristics of Generators and Receivers for Use in BalancedDigital Multipoint Systems.RS-485 is commonly used,rather than its official title.If more than one driver isrequired,devices conforming to RS-485 are recommended.RS-485 specifications allow only one driver tosend data at a time,and up to 32 unit loads(U.L.)can be placed on the bus.The U.L.concept isdescribed in this application report in the Selected RS-485 Electrical Specifications section.RS-422 and RS-485 initially might appear to be similar,but are distinct,and interchangeability isdetermined by the bus architecture.The RS-485 standard is written to be electrically compatible withRS-422.To illustrate their basic differences,a condensed description of each standard is presented in thefollowing subsections.2.1Selected RS-422 Electrical SpecificationsThe balanced-voltage digital interface is shown in Figure 1.The driver(or generator)is labeled D,thereceiver is labeled R,and the termination impedance is ZT.The termination impedance should be equal tothe characteristic impedance of the cable,Zo,and is used only once at the end of the cable.Becausematching termination impedance to Zooften is difficult to achieve and is application dependent,typically,20%is sufficient.Also,up to nine additional receivers can be placed along the cable from points A and Bto points A and B,respectively.No restriction on maximum cable length is imposed by the RS-422standard.Taking this into account,systems of up to 1 km are not uncommon,with signaling rates nohigher than about 100 kbps.Speed and cable lengths work against each other.In other words,the longerthe cable,the slower the signaling rate must be,while data can be transmitted faster on shorter cables.Asa rule of thumb,the data signaling rate(in bps)multiplied by the cable length(in meters)should notexceed 108.For example,a system with a cable measuring 500 m should not transmit data at speedsgreater than 200 kbps(108/500).3SLLA070DJune 2002Revised May 2010RS-422 and RS-485 Standards Overview and System ConfigurationsCopyright 20022010,Texas Instruments IncorporatedZTABABLogic(1?or?0)RDS0450-01Logic(1?or?0)DAB+VOAS0451-01VOD+VOB+Overview of RS-422 and RS-485 SAD=driver(or generator)BR=receiverCZT=termination impedanceFigure 1.RS-422 Balanced-Voltage Digital-Interface CircuitAlthough the input electrical characteristics of the RS-422-compliant receiver are identical to those of theRS-423-compliant receiver(ANSI TIA/EIA-423 standard),the RS-423 specifies an unbalanced signalingscheme,which is not within the scope of this application report.Descriptions of selected specified parameters are presented in the following paragraphs.2.1.1Open-Circuit Output Voltage(VOD,VOA,and VOBMeasured)The output voltage shall not exceed 6 V under unloaded conditions,and the differential voltagemeasured as the difference between an output voltage,VOA(VOB),and its complementary output voltage,VOB(VOA)is no greater than 10 V.See Figure 2 for the test circuit.A|VOD|10 V,|VOA|6 V,and|VOB|6 VBVOA=voltage on A outputCVOB=voltage on B outputDVOD=differential output voltageFigure 2.RS-422 Open-Circuit Test Circuit2.1.2Differential and Offset Output Voltage(VODand VOCMeasured)To ensure proper drive strength,a minimum of 2-V VODand a maximum of 3-V VOSare measured(seeFigure 3).Furthermore,a check on driver output-voltage balance between the differential output voltagesis put in place to measure the change in these voltages(not to exceed 400 mV).The maximum limit of400 mV most often is approached during transients when driver outputs are switching states.4RS-422 and RS-485 Standards Overview and System ConfigurationsSLLA070DJune 2002Revised May 2010Copyright 20022010,Texas Instruments IncorporatedLogic(1?or?0)DAB50 WVOD+VOC50 WA.?VOD|?2?V,?|V|?3?VB.?|V|?=?|V|?-?V|?0.4?VC.OSODODODD|V|?=?|V|?-?V|?0.4?VDOCOCOCLogic(1 or 0)DABIOCS0453-01IOCLogic(1?or?0)DABIOFFIOFFvOvOS0454-Overview of RS-422 and RS-485 StandardsFigure 3.RS-422 Output-Voltage Test Circuit2.1.3Short-Circuit Output Current(IOSMeasured)With the driver shorted to ground,the magnitude of the output current shall not exceed 150 mA,regardless of the state of the driver output(high or low)at the time of the short.This test ensures that thedevice is not destroyed by excessive current flowing through the output stage.Figure 4 shows the testcircuit.A|IOC|to ground 150 mAFigure 4.RS-422 Short-Circuit Output-Current Test Circuit2.1.4Power-Off Measurement(IOFFMeasured;VOApplied)As shown in Figure 5,with the driver powered down,the magnitude of the output leakage current shall notexceed 100 A for output voltages ranging from 0.25 V to 6 V.Currents higher than 100 A can disruptthe bus potential and lead to erroneous data at the receiver.A|Ioff|100 A for 0.25 VO 6 VFigure 5.RS-422 Power-Off Output-Current Test Circuit5SLLA070DJune 2002Revised May 2010RS-422 and RS-485 Standards Overview and System ConfigurationsCopyright 20022010,Texas Instruments Incorporated1.1 VSS1.1 VSS0.1 VSStuitrtf0.1 VSS0.9 VSS0-V DifferentialVODLogic(1 or 0)DAB100 WS0455-01VOD+VSSVOD0.9 VSSA.t=time duration of the unit intervalB.V=|V-V|C.2 V|V|10 VuiSSODODOD?Overview of RS-422 and RS-485 S2.1.5Output-Signal Waveform(VODMeasured)Basically,this test ensures good signal quality on the bus.With a 100-resistor across the differentialoutput,the voltage monotonically changes between 10%and 90%of VSSwithin a tenth of the unit interval,tui,or 20 ns,whichever is greater.Figure 6 shows the test circuit and resultant waveform.In addition,theresultant voltage shall not change more than 10%of VSSafter a transition has occurred(limits overshootsand undershoots).Figure 6.RS-422 Test Circuit and Output-Signal Waveform2.1.6Input I/V Characteristics(VIA,and VIB,Applied;IIA,and IIB,Measured)A maximum limit on the input characteristic must be placed on the receiver to ensure a maximum load onthe bus when all ten receivers are placed on it.With the common-mode voltage VIA,(VIB)ranging from+10V to 10 V while VIB,(VIA,)is held to 0 V,the resultant input current should remain within the shadedregion(see Figure 7)in both the power-on and power-off conditions.A device with input characteristicswithin the shaded region reveals that the input impedance is no smaller than 4 k,as defined by thecalculation.The inverse of the slope of the upper and lower bounds is exactly the minimum inputimpedance allowed for the input.6RS-422 and RS-485 Standards Overview and System ConfigurationsSLLA070DJune 2002Revised May 2010Copyright 20022010,Texas Instruments IncorporatedS0456-01RABIIBIIAvIAvIB+3V3V+10V10V3.25?mA3.25 mAVIIIOverview of RS-422 and RS-485 StandardsAR=V/I=13 V/3.25 mA=4 kFigure 7.RS-422 Input Receiver Test Circuit and I/V Plot2.1.7Input Sensitivity(VCM,VIA,and VIB,Applied;VIDMeasured)Figure 8 shows the test circuit used to determine a receivers input sensitivity.To ensure functionality overthe full common-mode range,suggested test voltages for both inputs and the purpose of themeasurements are given in Table 1.7SLLA070DJune 2002Revised May 2010RS-422 and RS-485 Standards Overview and System ConfigurationsCopyright 20022010,Texas Instruments IncorporatedS0457-01RABIIBIIAvIAvIB+1010+200 mV200?mVVIDVIDTransitionRegionMaximumOperatingRangeOverview of RS-422 and RS-485 SA200 mV|VID|10 VFigure 8.RS-422 Input-Sensitivity Test Circuit and Resultant WaveformFor a common-mode voltage varying from 7 V to 7 V,VIDneed not be greater than 200 mV to correctlyassume the intended state.As specified in the standard,the magnitude of the differential input voltage,VID,varying from 200 mV to 10 V,is required to maintain correct operation over this range.Table 1.Input Sensitivity and Resultant Voltages of 422-Compliant DevicesAPPLIED VOLTAGERECEIVERRESULTINGRESULTINGOUTPUTPURPOSE OF MEASUREMENTSVID(1)VCM(2)VIA(3)VIB(3)STATE+10 V2 V+12 V+4 VQEnsures correct operation with maximum differentialvoltage supply10 V+2 V12 V4 VQ+10 V+4 V+6 V+7 VQEnsures correct operation with maximum common modevoltage supply10 V4 V6 V7 VQ+100 mV100 mV+200 mV0 VQ100 mV+100 mV200 mV0 VQ200 mV threshold test across common mode voltagesupply+7.1 V+6.9 V+200 V+7 VQ7.1 V6.9 V200 V7 VQ(1)|VID|12 V(maximum input differential voltage without damaging device)(2)VCMis measured as the arithmetic average of VIAand VIB,or(VIA+VIB)/2.(3)|VIA|10 V,|VIB|4tdelay,the cable is notconsidered a transmission line.)Figure 17.Differential Unterminated-Driver Output WaveformsFigure 18.Differential Unterminated-Receiver Input Waveforms4.2Parallel TerminationFigure 19 shows a typical configuration using an impedance termination across the differential inputs atthe far-end receiver.As shown in Figure 20 and Figure 21,parallel termination ensures that there are noimpedance mismatches and eliminates reflections.A termination resistance of 100 was applied,andonly one receiver was used in this experiment,while transmitting at a data signaling rate of 1 Mbps.14RS-422 and RS-485 Standards Overview and System ConfigurationsSLLA070DJune 2002Revised May 2010Copyright 20022010,Texas Instruments IncorporatedZTROUTDINRRDS0464-01DYRBRADZLSTUBG003DINDZDYROUTSuggested Termination and Grounding TechniquesAZT=ZoFigure 19.Differential Parallel-Terminated ConfigurationAdvantagesElimination of reflections:higher data rates and longer cablesMultidrop applications are also supported.DisadvantagesLong stub lengths(LSTUB)reintroduce reflections.Increase in drivers power dissipation(when compared to the unterminated case)Receivers differential input is zero when all drivers are idle.Figure 20.Differential Parallel-Terminated Driver Output Waveforms15SLLA070DJune 2002Revised May 2010RS-422 and RS-485 Standards Overview and System ConfigurationsCopyright 20022010,T