IEC_62530-2011_IEEE_Std_1800.pdf

IEC 62530 Edition 2.0 2011-05 INTERNATIONAL STANDARD SystemVerilog Unified Hardware Design,Specification,and Verification Language IEC 62530:2011(E)IEEE Std 1800-2009 IEEE Std 1800 colourinsideCopyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,,downloaded on Nov-28-2014 by James Madison.No further reproduction or distribution is permitted.Uncontrolled when printed.THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2009 IEEE All rights reserved.IEEE is a registered trademark in the U.S.Patent&Trademark Office,owned by the Institute of Electrical and Electronics Engineers,Inc.Unless otherwise specified,no part of this publication may be reproduced or utilized in any form or by any means,electronic or mechanical,including photocopying and microfilm,without permission in writing from the IEC Central Office.Any questions about IEEE copyright should be addressed to the IEEE.Enquiries about obtaining additional rights to this publication and other information requests should be addressed to the IEC or your local IEC member National Committee.IEC Central Office The Institute of Electrical and Electronics Engineers,Inc 3,rue de Varemb 3 Park Avenue CH-1211 Geneva 20 US-New York,NY10016-5997 Switzerland USA Email:inmailiec.ch Email:stds-infoieee.org Web:www.iec.ch Web:www.ieee.org About the IEC The International Electrotechnical Commission(IEC)is the leading global organization that prepares and publishes International Standards for all electrical,electronic and related technologies.About IEC publications The technical content of IEC publications is kept under constant review by the IEC.Please make sure that you have the latest edition,a corrigenda or an amendment might have been published.Catalogue of IEC publications:www.iec.ch/searchpub The IEC on-line Catalogue enables you to search by a variety of criteria(reference number,text,technical committee,).It also gives information on projects,withdrawn and replaced publications.IEC Just Published:www.iec.ch/online_news/justpub Stay up to date on all new IEC publications.Just Published details twice a month all new publications released.Available on-line and also by email.Electropedia:www.electropedia.org The worlds leading online dictionary of electronic and electrical terms containing more than 20 000 terms and definitions in English and French,with equivalent terms in additional languages.Also known as the International Electrotechnical Vocabulary online.Customer Service Centre:www.iec.ch/webstore/custserv If you wish to give us your feedback on this publication or need further assistance,please visit the Customer Service Centre FAQ or contact us:Email:csciec.ch Tel.:+41 22 919 02 11 Copyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,,downloaded on Nov-28-2014 by James Madison.No further reproduction or distribution is permitted.Uncontrolled when printed.IEC 62530Edition 2.0 2011-05INTERNATIONAL STANDARD SystemVerilog Unified Hardware Design,Specification,and Verification Language INTERNATIONAL ELECTROTECHNICAL COMMISSION XXICS 25.040 PRICE CODEISBN 978-2-88912-450-3 IEEE Std 1800 colourinsideCopyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,,downloaded on Nov-28-2014 by James Madison.No further reproduction or distribution is permitted.Uncontrolled when printed.Copyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,,downloaded on Nov-28-2014 by James Madison.No further reproduction or distribution is permitted.Uncontrolled when printed.-i-IEC 62530:2011(E)IEEE Std 1800-2009Published by IEC under license from IEEE.2009 IEEE.All rights reserved.Contents Part One:Design and Verification Constructs1.Overview.21.1Scope.21.2Purpose.21.3Merger of IEEE Std 1364-2005 and IEEE Std 1800-2005.31.4Special terms.31.5Conventions used in this standard.31.6Syntactic description.41.7Use of color in this standard.51.8Contents of this standard.51.9Deprecated clauses.81.10 Examples.81.11 Prerequisites.82.Normative references.93.Design and verification building blocks.113.1General.113.2Design elements.113.3Modules.113.4Programs.123.5Interfaces.133.6Checkers.143.7Primitives.143.8Subroutines.143.9Packages.143.10 Configurations.153.11 Overview of hierarchy.153.12 Compilation and elaboration.163.13 Name spaces.183.14 Simulation time units and precision.194.Scheduling semantics.234.1General.234.2Execution of a hardware model and its verification environment.234.3Event simulation.234.4The stratified event scheduler.244.5The SystemVerilog simulation reference algorithm.294.6Determinism.294.7Nondeterminism.304.8Race conditions.304.9Scheduling implication of assignments.304.10 The PLI callback control points.325.Lexical conventions.335.1General.335.2Lexical tokens.335.3White space.335.4Comments.335.5Operators.335.6Identifiers,keywords,and system names.345.7Numbers.355.8Time literals.40Copyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,,downloaded on Nov-28-2014 by James