ASTM_F_1771_-_97.pdf

Designation:F 1771 97Standard Test Method forEvaluating Gate Oxide Integrity by Voltage RampTechnique1This standard is issued under the fixed designation F 1771;the number immediately following the designation indicates the year oforiginal adoption or,in the case of revision,the year of last revision.A number in parentheses indicates the year of last reapproval.Asuperscript epsilon(e)indicates an editorial change since the last revision or reapproval.1.Scope1.1 The techniques outlined in this standard are for thepurpose of standardizing the procedure of measurement,analy-sis,and reporting of oxide integrity data between interestedparties.This test method makes no representation regardingactual device failure rates or acceptance/rejection criteria.While some suggestions for data analysis are included in latersections of this test method,interpretation of results is beyondthe scope of this standard.Any such interpretations should beagreed upon between interested parties prior to testing.Forexample,a variety of failure criteria are included to permitseparation of so-called intrinsic and extrinsic oxide failures.1.2 This test method covers the procedure for gaging theelectrical strength of silicon dioxide thin films with thicknessesranging from approximately 3 nm to 50 nm.In the analysis offilms of 4 nm or less,the impact of direct tunneling on thecurrent-voltage characteristics,and hence the specified failurecriteria defined in 5.4,must be taken into account.Since oxideintegrity strongly depends on wafer defects,contamination,cleanliness,as well as processing,the users of this test methodare expected to include wafer manufacturers and devicemanufacturers.1.3 This test method is not structure specific,but notesregarding options for different structures may be found in theappendix.The three most likely structures are simple planarmetal-oxide semiconductor(MOS-capacitors)(fabricated ormercury probe),various isolation structures(for example,localoxidation of silicon(LOCOS),and field effect transistors.Thistest method assumes that a low resistance ohmic contact ismade to the backside of each wafer in each case.For a moredetailed discussion of the design and evaluation of test struc-tures for this test method,the reader is referred to theEIA/JEDEC Standard 35-1.21.4 Failure criteria specified in this test method include boththe fixed current limit(soft)and destructive(hard)types.In thepast,use of a fixed current limit of 1 A or more virtuallyensured measurement of hard failure,as the thicker,moreheavily contaminated oxides of those days typically failedcatastrophically as soon as measurable currents were passed.The cleaner processing of thinner oxides now means thatoxides will sustain relatively large currents with little or noevidence of failure.While use of fixed current limit testing maystill be of value for assessing uniformity issues,it is widely feltthat failure to continue oxide breakdown testing to the point ofcatastrophic oxide failure may mask the presence of defecttails,which are of critical importance in assessing long-termoxide reliability.For this reason,this test method makesprovision for use of fixed limit failure criteria if desired andagreed upon by the parties to the testing,but specifies thattesting be continued until hard failure is sensed.1.5 This test method specifically does not include measure-ment of a charge-to-breakdown(Qbd)parameter.Industryexperience with this parameter measured in a ramp-to-failuretest such as this indicates that Qbdvalues so obtained may beunreliable indicators of oxide quality.This is because a largefraction of the value determined is collected in the last steps ofthe test,and the result is subject to large deviations.Qbdshouldbe measured in a constant current or bounded current ramp test.1.6 This test method is applicable to both n-type and p-typewafers,polished or having an epitaxial layer.In wafers withepitaxial layers,the conductivity type of the layer should be thesame as that of the bulk wafer.While not excluding depletionpolarity,it is preferred that measurement polarity should be inaccumulation to void the complication of a voltage drop acrossthe depletion layer.1.7 While this test method is primarily intended for use incharacterizing the SiO2-silicon systems as stated above,it maybe applied in general terms to the measurement of othermetal-insulator-semiconductor structures if appropriate consid-eration of the characteristics of the other materials is made.1.8 Measurement conditions specified in this test methodare conservative,intended for thorough analysis of high qualityoxide-silicon systems,and to provide a regime in which newusers may safely begin testing without encountering undueexperimental artifacts.It is recognized that some experiencedusers may be working in applications where less precise data isrequired and a more rapid test is desirable.An example of thissituation is the evaluation of silicon wafer quality,where astaircase voltage step providin