ASTM_F_1809_-_97.pdf

Designation:F 1809 97Standard Guide forSelection and Use of Etching Solutions to DelineateStructural Defects in Silicon1This standard is issued under the fixed designation F 1809;the number immediately following the designation indicates the year oforiginal adoption or,in the case of revision,the year of last revision.A number in parentheses indicates the year of last reapproval.Asuperscript epsilon(e)indicates an editorial change since the last revision or reapproval.1.Scope1.1 This guide covers the formulation,selection,and use ofchemical solutions developed to reveal structural defects insilicon wafers.Etching solutions identify crystal defects thatadversely affect the circuit performance and yield of silicondevices.Sample preparation,temperature control,etching tech-nique,and choice of etchant are all key factors in the successfuluse of an etching method.This guide provides information forseveral etching solution and allows the user to select accordingto the need.For further information see Appendix X1and Figs.1-32.For a test method for counting preferentially etched ordecorated surface defects in silicon wafers see Test MethodF 1810.1.2 This standard does not purport to address all of thesafety concerns,if any,associated with its use.It is theresponsibility of the user of this standard to establish appro-priate safety and health practices and determine the applica-bility of regulatory limitations prior to use.2.Referenced Documents2.1 ASTM Standards:D 5127 Practice for Electronic Grade Water2F 1725 Guide forAnalysis of Crystallographic Perfection inSilicon Ingots3F 1726 Guide forAnalysis of Crystallographic Perfection inSilicon Wafers3F 1727 Practice for Detection of Oxidation Induced Defectsin Polished Silicon Wagers3F 1810 Method for Counting Preferentially Etched or Deco-rated Surface Defects in Silicon Wafers32.2SEMI Specifications:SEMI C-1 Specification for Reagents43.Significance and Use3.1 Structural defects formed in the bulk of a silicon waferduring its growth or induced by electronic device processingcan affect the performance of the circuitry fabricated on thatwafer.These defects take the form of dislocations,slip,stacking faults,shallow pits,or precipitates.3.2 The exposure of the various defects found on or in asilicon wafer is often the first critical step in evaluating waferquality or initiating failure analysis of an errant device struc-ture.Etching often accomplishes this task.4.Interferences4.1 Complicating factors are different for each etchant.Research the choice of etchants in advance to ensure the1This guide is under the jurisdiction of ASTM Committee F01 on Electronicsand is the direct responsibility of Subcommittee F01.06 on Silicon Materials andProcess Control.Current edition approved June 10,1997.Published August 1997.2Annual Book of ASTM Standards,11.013Annual Book of ASTM Standards,Vol 10.05.4Available from Semiconductor Equipment and Materials International,805 E.Middlefield Rd.,Mountain View,CA 94043.FIG.1 Secco Etch With Agitation,Oxidation Stacking Fault,1000 x,100,(1100C Steam,80 minutes),;4 m removal.FIG.2 Secco Etch With Agitation,Oxidation Stacking Fault,400 x,100,(1100C Steam,80 minutes),;4 m removal.1Copyright ASTM International,100 Barr Harbor Drive,PO Box C700,West Conshohocken,PA 19428-2959,United States.method and solution are compatible with the sample andobjectives.Commonly encountered problems are:4.1.1 Inadvertent etching through the denuded zone of anoxidized sample delineates irrelevant bulk defects instead ofthe surface oxidation induced stacking faults(OISF)expected.4.1.2 Accelerated etching and etching artifacts can resultfrom excessive solution heating during the etching process.4.1.3 Insufficient agitation,bubble formation or particles inthe etching solution can generate artifacts on the silicon surfacethat mimic actual defects.Insufficient agitation can alter theetching rate,increasing or decreasing it depending upon theformulation.4.1.4 Any solution in which the oxidation rate is greaterthan the oxide dissolution rate may form oxide layers that slowor even quench the etching process.The presence of theseoxide layers(especially for N+and P+material)obstructs theinterpretation of etched defects.Before evaluation,remove anysurface oxides.4.1.5 The wafer surface becomes rougher with longer etchtime.This rougher surface does not prevent evaluation underthe microscope,but it greatly reduces the effectiveness ofvisual inspection under bright light.FIG.3 Secco Etch Without Agitation,Flow Pattern Defect 200 x,100,;8 m removal.FIG.4 Secco Etch With Agitation,Expitaxial Stacking Fault,150 x,100,;4 m removal.FIG.5 Secco Etch With Agitation,Bulk Oxidation Stacking Fault,200 x,100,(1100C Steam,80 minutes),;15 m removal.FIG.6 Secco Etch With Agitation,Scratch Induced OxidationStacking Faults,100 x,100,(1100C Steam,80 minutes),;15 mremoval.FIG.7 Wright Etch With Agitation,Damaged Induced OxidationStacking Fault,1000 x,100,(1100C Steam,80 minutes).FIG.8 Wright Etch