ASTM_F_615M_-_95_2013.pdf

Designation:F615M95(Reapproved 2013)Standard Practice forDetermining Safe Current Pulse-Operating Regions forMetallization on Semiconductor Components(Metric)1This standard is issued under the fixed designation F615M;the number immediately following the designation indicates the year oforiginal adoption or,in the case of revision,the year of last revision.A number in parentheses indicates the year of last reapproval.Asuperscript epsilon()indicates an editorial change since the last revision or reapproval.1.Scope1.1 This practice covers procedures for determining operat-ing regions that are safe from metallization burnout induced bycurrent pulses of less than 1-s duration.NOTE1In this practice,“metallization”refers to metallic layers onsemiconductor components such as interconnect patterns on integratedcircuits.The principles of the practice may,however,be extended tonearly any current-carrying path.The term“burnout”refers to eitherfusing or vaporization.1.2 This practice is based on the application of unipolarrectangular current test pulses.An extrapolation technique isspecified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane.Aprocedure is providedin Appendix X2 to relate safe operating regions establishedfrom rectangular pulse data to safe operating regions forarbitrary pulse shapes.1.3 This practice is not intended to apply to metallizationdamage mechanisms other than fusing or vaporization inducedby current pulses and,in particular,is not intended to apply tolong-term mechanisms,such as metal migration.1.4 This practice is not intended to determine the nature ofany defect causing failure.1.5 This standard does not purport to address all of thesafety concerns,if any,associated with its use.It is theresponsibility of the user of this standard to establish appro-priate safety and health practices and determine the applica-bility of regulatory limitations prior to use.2.Terminology2.1 Definitions of Terms Specific to This Standard:2.1.1 failurea change in the measured resistance of610%R/R or as agreed upon by the parties to the test.3.Summary of Practice3.1 Specimens are selected from the population being evalu-ated.3.2 The d-c resistance of each specimen is measured.3.3 Each specimen is subjected to stress from rectangularcurrent pulses varying in amplitude and duration according toa predetermined schedule of pulse width and amplitudes.3.4 A second d-c resistance measurement is made on eachspecimen after each pulse,and it is characterized as havingfailed or survived.3.5 The number,x,of specimens surviving and the totalnumber,n,of specimens tested at each pulse width andamplitude are analyzed statistically to determine the burnoutlevel at each test pulse width for the desired burnout survivalprobability and confidence level.3.6 A point corresponding to the burnout level(at thedesired probability and confidence level)is plotted for each ofthe test pulse duration values in the pulse-amplitude,pulse-duration plane.Based on these points,an extrapolation tech-nique is used to plot the boundary of the safe operating region.3.7 The following items are not specified by the practice andare subject to agreement by the parties to the test:3.7.1 The procedure by which the specimens are to beselected.3.7.2 Test patterns that will be representative of adjacentmetallization on a die or wafer(5.3).3.7.3 The schedule of pulse amplitudes and durations to beapplied to the test samples(9.8).3.7.4 The level of probability and confidence to be used incalculations to establish the boundary of the safe operatingregion(10.1).3.7.5 The amount of change of resistance that will define thecriterion for failure.3.7.6 The statistical model to be used to determine theburnout probability at a desired stress level.3.7.7 The form and content of the report.4.Significance and Use4.1 Solid-state electronic devices subjected to stresses fromexcessive current pulses sometimes fail because a portion ofthe metallization fuses or vaporizes(suffers burnout).Burnoutsusceptibility can vary significantly from component to com-ponent on a given wafer,regardless of design.This practice1This practice is under the jurisdiction of ASTM Committee F01 on Electronicsand is the direct responsibility of Subcommittee F01.11 on Nuclear and SpaceRadiation Effects.Current edition approved May 1,2013.Published May 2013.Originallyapproved in 1995.Last previous edition approved in 2008 as F615M-95(2008).DOI:10.1520/F0615M-95R13.Copyright ASTM International,100 Barr Harbor Drive,PO Box C700,West Conshohocken,PA 19428-2959.United States1 provides a procedure for establishing the limits of pulse currentoverstress within which the metallization of a given deviceshould survive.4.2 This practice can be used as a destructive test in alot-sampling program to determine the boundaries of the safeoperating region having desired survival probabilities andstatistical confidence levels when appropriate sample quantitiesand statistical analyses are