ASTM_F_1260M_-_96_2003.pdf

Designation:F 1260M 96(Reapproved 2003)METRICStandard Test Methodfor Estimating Electromigration Median Time-To-Failure andSigma of Integrated Circuit Metallizations Metric1This standard is issued under the fixed designation F 1260M;the number immediately following the designation indicates the year oforiginal adoption or,in the case of revision,the year of last revision.A number in parentheses indicates the year of last reapproval.Asuperscript epsilon(e)indicates an editorial change since the last revision or reapproval.1.Scope1.1 This test method is designed to characterize the failuredistribution of interconnect metallizations such as are used inmicroelectronic circuits and devices that fail due to electromi-gration under specified d-c current density and temperaturestress.This test method is intended to be used only when thefailure distribution can be described by a log-Normal distribu-tion.1.2 This test method is intended for use as a referee methodbetween laboratories and for comparing metallization alloysand metallizations prepared in different ways.It is not intendedfor qualifying vendors or for determining the use-life of ametallization.1.3 The test method is an accelerated stress test of four-terminal structures(see Guide F 1259M)where the failurecriterion is either an open circuit in the test line or a prescribedpercent increase in the resistance of the test structure.1.4 This test method allows the test structures of a test chipto be stressed while still part of the wafer(or a portion thereof)or while bonded to a package and electrically accessible bymeans of package terminals.1.5 This test method is not designed to characterize themetallization for failure modes involving short circuits be-tween adjacent metallization lines or between two levels ofmetallization.1.6 This test method is not intended for the case where thestress test is terminated before all parts have failed.1.7 This test method is primarily designed to analyzecomplete data.An option is provided for analyzing censoreddata(that is,when the stress test is halted before all parts undertest have failed).1.8 This standard does not purport to address all of thesafety concerns,if any,associated with its use.It is theresponsibility of the user of this standard to establish appro-priate safety and health practices and determine the applica-bility of regulatory limitations prior to use.2.Referenced Documents2.1 ASTM Standards:F 1259MGuide for Design of Flat,Straight-Line TestStructures for Detecting Metallization Open-Circuit orResistance-Increase Failure due to Electromigration Met-ric2F 1261MTest Method for Determining the Average Elec-trical Width of a Straight,Thin-Film Metal Line Metric22.2Other Standards:EIA/JEDEC Standard 33-A Standard Method for Mea-suring and Using the Temperature Coefficient of Resis-tance to Determine the Temperature of a MetallizationLine3EIA/JEDEC Standard 37 Lognormal Analysis of Uncen-sored Data,and of Singly Right-Censored Data Utilizingthe Persson and Rootzen Method33.Terminology3.1 Definitions of Terms Specific to This Standard:3.1.1 metallizationthe thin-film metallic conductor usedas electrical interconnects in a microelectronic integratedcircuit.3.1.2 test chipan area on a wafer containing one or moretest structures that are stressed according to the test methodwhile either is still part of the wafer or after having beenseparated and packaged.3.1.3 test linea straight metallization line of designeduniform width that is subjected to the current density andtemperature stresses prescribed in the test method.3.1.4 test structurea passive metallization structure,withterminals to permit electrical access,that is fabricated on asemiconductor wafer by the normal procedures used to manu-facture microelectronic integrated devices.1This test method is under the jurisdiction of ASTM Committee F01 onElectronics and is the direct responsibility of Subcommittee F01.11 on Quality andHardness Assurance.Current edition approved June 10,1996.Published August 1996.Originallypublished as F 1260 89.Last previous edition F 1260 89.2Annual Book of ASTM Standards,Vol 10.04.3Available from Global Engineering,15 Inverness Way,East Inglewood,CO80112-5776.1Copyright ASTM International,100 Barr Harbor Drive,PO Box C700,West Conshohocken,PA 19428-2959,United States.4.Summary of Test Method4.1 This test method is used to obtain sample estimates ofthe median-time-to-failure,t50,and sigma that describe thefailure distribution of metallization test lines subjected tocurrent density and temperature stress.This involves subject-ing a sample of N test structures to high current density andhigh ambient temperature stress,calculating the stress tempera-ture of the metallization during the test,(which takes accountof joule heating)and measuring the time to failure of eachstructure.The time-to-fail of the test structures is empiricallydescribed by a log-Normal distribution.The sample estimate oft50is equal to the exponential of the mean of the