ASTM_F_1152_-_93_2001.pdf

Designation:F 1152 93(Reapproved 2001)Standard Test Method forDimensions of Notches on Silicon Wafers1This standard is issued under the fixed designation F 1152;the number immediately following the designation indicates the year oforiginal adoption or,in the case of revision,the year of last revision.A number in parentheses indicates the year of last reapproval.Asuperscript epsilon(e)indicates an editorial change since the last revision or reapproval.1.Scope1.1 This test method covers a nondestructive procedure todetermine whether or not the dimensions of fiducial notches onsilicon wafers fall within specified limits.1.2 The values stated in SI units are to be regarded as thestandard.The values given in parentheses are for informationonly.1.3 This standard does not purport to address all of thesafety concerns,if any,associated with its use.It is theresponsibility of the user of this standard to establish appro-priate safety and health practices and determine the applica-bility of regulatory limitations prior to use.2.Referenced Documents2.1 ASTM Standards:E 122 Practice for Choice of Sample Size to Estimate aMeasure of Quality of a Lot or Process22.2Military Standard:MIL-STD-105E Sampling Procedures and Tables for In-spection by Attributes32.3SEMI Standard:M 1 Specifications for Monocrystalline Silicon Wafers43.Summary of Test Method3.1 The wafer is aligned in position on an optical compara-tor and the image of the notch is compared with a series oftemplates projected on the screen of the comparator.3.2 First,the wafer is aligned so that the sides of the imageof the notch contact the image of the alignment pin used to fixthe position of the wafer in use.In this case,the image of thenotch bottom must lie on or below the designated line on thenotch form/depth template and the image of the wafer edgemust lie on or above another designated line on the template.3.3 The wafer is then aligned so that the image of the waferedge coincides with the wafer periphery line on the template.In this case the image of the notch bottom must lie betweenmaximum and minimum lines on the template.3.4 The image of the notch sides are compared with a seriesof angles on the notch angle template and the angle that makesthe best fit is chosen as the value of the notch angle.3.5 No test is provided for the blend radius at the apex of thenotch.4.Significance and Use4.1 Wafers must be accurately aligned in various processingequipment during integrated circuit manufacture.4.2 A notch ground into the edge of the wafer at a specifiedorientation provides a positive method for such alignment.Theaccuracy of the critical dimensions of the notch controls thepossible accuracy of the alignment.4.3 This test method is specifically directed to the notchdimensions specified in SEMI Specifications M 1,but withsuitable modifications,the principles of this test method maybe applied to any desired notch dimensions.4.4 This test method may be used for process control,quality control,and incoming or outgoing inspection.4.5 Until an index of precision is determined based on aninterlaboratory evaluation,this test method is not recom-mended for use in decisions between purchasers and suppliers.5.Interferences5.1 Any foreign material or rough spots on the notch edge inthe light path may present a distorted image which can result inthe determination of incorrect dimensions.5.2 Alignment of the notch position with respect to thecenter of the wafer is important in achieving an accuratedetermination of the notch characteristics.5.3 Wear of grinding tools and process variations may resultin notch edges which are not exactly straight and a nonuniqueradius at the apex of the notch.Under these conditions,greatcare must be taken to align the image of the notch correctlyagainst the appropriate portions of the template.6.Apparatus6.1 Optical Comparator,capable of 20 and 503 magnifi-cation with a viewing screen large enough to display an area 5by 5 mm at 203 or 2 by 2 mm at 503.6.2 Fixture,for holding the wafer to be tested.The fixturemust provide means for positioning the wafer such that theplane of the surface of the wafer is perpendicular to theviewing direction and that the wafer can be rotated about itscenter.The horizontal and vertical motions are parallel or1This test method is under the jurisdiction of ASTM Committee F01 onElectronics and is the direct responsibility of Subcommittee F01.06 on SiliconMaterials and Process Control.Current edition approved Aug.15,1993.Published October 1993.Originallypublished as F 1152 88.Last previous edition F 1152 88.2Annual Book of ASTM Standards,Vol 14.02.3Available from Standardization Documents Order Desk,Bldg.4 Section D,700Robbins Ave.,Philadelphia,PA 19111-5094,Attn:NPODS.4Available from the Semiconductor Equipment and Materials Institute,805Middlefield Rd.,Mountain View,CA 94043.1Copyright ASTM,100 Barr Harbor Drive,West Conshohocken,PA 19428-2959,United States.perpendicular to the diameter of the wafer that passes throug