ASTM_F_1049_-_00.pdf

Designation:F 1049 00Standard Practice forShallow Etch Pit Detection on Silicon Wafers1This standard is issued under the fixed designation F 1049;the number immediately following the designation indicates the year oforiginal adoption or,in the case of revision,the year of last revision.A number in parentheses indicates the year of last reapproval.Asuperscript epsilon(e)indicates an editorial change since the last revision or reapproval.1.Scope1.1 This practice is used to detect shallow etch pits,whichmay be related to the level of metallic impurities near thesurface of silicon epitaxial or polished wafers.1.2 This practice is not recommended for use in defectdensity evaluations,but as a subjective means of estimatingdefect densities and distributions on the surface of a polished orepitaxial wafer.1.3 Silicon crystals doped either p-or n-type and withresistivities as low as 0.005 Vcm may be evaluated.Thispractice is applicable for silicon wafers grown in either a(111)or(100)crystal orientation.1.4 This practice utilizes a thermal oxidation process fol-lowed by a chemical preferential etchant to create and thendelineate shallow etch pits.1.5 The values stated in acceptable metric units are to beregarded as the standard.The values in parentheses are forinformation only.1.6 This standard does not purport to address all of thesafety concerns,if any,associated with its use.It is theresponsibility of the user of this standard to establish appro-priate safety and health practices and determine the applica-bility of regulatory limitations prior to use.Specific hazardstatements are given in Section 9.2.Referenced Documents2.1 ASTM Standards:D 5127 Guide for Electronic Grade Water2F 154 Guide for Identification of Structures and Contami-nants Seen on Specular Silicon Surfaces3F 1725 Guide forAnalysis of Crystallographic Perfection ofSilicon Ingots3F 1727 Practice for Dection of Oxidation Induced Defectsin Polished Silicon Wafers3F 1809 Guide for Selection and Use of Etching Solutions toDelineate Structural Defects in Silicon3F 1810 Test Method for Counting Preferentially Etched orDecorated Surface Defects in Silicon Wafers32.2SEMI Standards:SEMI C 1 Specifications for Reagents4M 17 Specification for a Universal Wafer Grid43.Terminology3.1 Definitions:3.1.1 hazeon a semiconductor wafer,nonlocalizedlight scattering resulting from surface topography(micror-oughness)or from dense concentrations of surface or near-surface imperfections.See also laser light scattering event.3.1.1.1 DiscussionHaze due to the existence of a collec-tion of imperfections of the type that result in haze cannot bereadily distinguished by the eye or other optical detectionsystem without magnification.In a scanning surface inspectionsystem,haze and laser-light scattering events comprise thelaser surface scanner signal due to light scattering from a wafersurface.3.1.2 shallow etch pitsetch pits that are small and shallowin depth under high magnification,2003.3.1.2.1 DiscussionShallow etch pits on silicon wafers areshown in Guide F 154.3.1.3 saucer pitssame as shallow etch pits,see 3.1.2.4.Summary of Practice4.1 Silicon wafers,either epitaxial or polished,are ther-mally oxidized and preferential etched.This will reveal smalletch pits,shallow in depth,when observed through an inter-ference contrast microscope.The distribution of the etch pitson the surface of the wafer are determined by illuminating thewafer with a high intensity lamp.5.Significance and Use5.1 High levels of etch pits are reported5to indicate metalliccontamination that is detrimental to wafer processing.This canbe deduced from the density of etch pits on the surface of thewafer.5.2 This practice is appropriate for process control,andresearch and development applications.Because its reproduc-ibility has not been established by interlaboratory test,it is notrecommended for use in materials acceptance unless the parties1This practice is under the jurisdiction of ASTM Committee F-1 on Electronicsand is the direct responsibility of Subcommittee F01.06 on Silicon Materials andProcess Control.Current edition approved June 10,2000.Published August 2000.Originallypublished as F 1049 87.Last previous edition F 1049 95.2Annual Book of ASTM Standards,Vol 11.01.3Annual Book of ASTM Standards,Vol 10.05.4Available from Semiconductor Equipment and Materials International,805 E.Middlefield Rd.,Mountain View,CA 94043.5Pearce,C.W.,and McMahon,R.G.,“Role of Metallic Contamination in theFormation of 8Saucer Pit Defects in Epitaxial Silicon,”Journal of Vacuum Scienceand Technology,Vol 14,No.1,1977,p.40.1Copyright ASTM,100 Barr Harbor Drive,West Conshohocken,PA 19428-2959,United States.to the test have conducted correlation experiments to establishthe precision to be expected.6.Interferences6.1 Etch artifacts are the primary cause of difficulty inidentifying shallow etch pits.Etch artifacts are generated invarious ways such as gas bubble formation during etching,improperly cleaned surface prior to etching,o